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path: root/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
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* Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng2011-07-011-2/+2
| | | | llvm-svn: 134244
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-281-2/+3
| | | | llvm-svn: 134030
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-1/+3
| | | | llvm-svn: 134024
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-5/+5
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Various bits of framework needed for precise machine-level selectionAndrew Trick2010-12-241-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. llvm-svn: 122541
* whitespaceAndrew Trick2010-12-241-29/+29
| | | | llvm-svn: 122539
* convert targets to the new MF.getMachineMemOperand interface.Chris Lattner2010-09-211-4/+6
| | | | llvm-svn: 114391
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-161-61/+0
| | | | llvm-svn: 108567
* Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling2010-07-161-1/+1
| | | | | | thus is a much more meaningful name. llvm-svn: 108563
* Emit COPY instead of FMR/FMSD instructions for floating point conversion onJakob Stoklund Olesen2010-07-161-1/+1
| | | | | | PowerPC. llvm-svn: 108555
* Teach PPCInstrInfo::storeRegToStackSlot and loadRegFromStackSlot to add memoryJakob Stoklund Olesen2010-07-161-0/+19
| | | | | | | | | operands. Hopefully this fixes the llvm-gcc-powerpc-darwin9 buildbot. It really shouldn't since missing memoperands should not affect correctness. llvm-svn: 108540
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-111-115/+0
| | | | | | | | The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. llvm-svn: 108099
* Replace copyRegToReg with copyPhysReg for PowerPC.Jakob Stoklund Olesen2010-07-111-30/+26
| | | | llvm-svn: 108083
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-171-7/+6
| | | | | | | | | | | | addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
* The PPC MFCR instruction implicitly uses all 8 of the CRDale Johannesen2010-05-201-1/+2
| | | | | | | | | | | | | | registers. Currently it is not so marked, which leads to VCMPEQ instructions that feed into it getting deleted. If it is so marked, local RA complains about this sequence: vreg = MCRF CR0 MFCR <kill of whatever preg got assigned to vreg> All current uses of this instruction are only interested in one of the 8 CR registers, so redefine MFCR to be a normal unary instruction with a CR input (which is emitted only as a comment). That avoids all problems. 7739628. llvm-svn: 104238
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-4/+2
| | | | | | doesn't have to guess. llvm-svn: 103194
* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-061-2/+4
| | | | llvm-svn: 103193
* No-ops emitted for scheduling don't correspond with anything in theDan Gohman2010-05-051-2/+0
| | | | | | user's source, so don't arbitrarily assign them a debug location. llvm-svn: 103121
* Frame index can be negative.Evan Cheng2010-04-291-1/+1
| | | | llvm-svn: 102577
* Add PPC specific emitFrameIndexDebugValue.Evan Cheng2010-04-261-0/+10
| | | | llvm-svn: 102325
* EnablePPC64RS and EnablePPC32RS are used in multiple files, so theyDan Gohman2010-04-151-1/+4
| | | | | | can't be static. llvm-svn: 101377
* Educate GetInstrSizeInBytes implementations thatDale Johannesen2010-04-071-0/+1
| | | | | | DBG_VALUE does not generate code. llvm-svn: 100681
* use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()Chris Lattner2010-04-021-5/+5
| | | | llvm-svn: 100214
* Teach AnalyzeBranch, RemoveBranch and the branchDale Johannesen2010-04-021-1/+14
| | | | | | | folder to be tolerant of debug info following the branch(es) at the end of a block. llvm-svn: 100168
* Merge PPC instructions FMRS and FMRD into a single FMR instruction.Jakob Stoklund Olesen2010-02-261-8/+6
| | | | | | | | | This is possible because F8RC is a subclass of F4RC. We keep FMRSD around so fextend has a pattern. Also allow folding of memory operands on FMRSD. llvm-svn: 97275
* Use the right floating point load/store instructions in ↵Jakob Stoklund Olesen2010-02-261-24/+14
| | | | | | | | | | | | | | | | | | PPCInstrInfo::foldMemoryOperandImpl(). The PowerPC floating point registers can represent both f32 and f64 via the two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to allow cross-class coalescing. This coalescing only affects whether registers are spilled as f32 or f64. Spill slots must be accessed with load/store instructions corresponding to the class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking at the instruction opcode which is wrong. X86 has similar floating point register classes, but doesn't try to fold memory operands, so there is no problem there. llvm-svn: 97262
* When save/restoring CR at prolog/epilog, in a largeDale Johannesen2010-02-121-14/+30
| | | | | | | | | | | | | | | | | stack frame, the prolog/epilog code was using the same register for the copy of CR and the address of the save slot. Oops. This is fixed here for Darwin, sort of, by reserving R2 for this case. A better way would be to do the store before the decrement of SP, which is safe on Darwin due to the red zone. SVR4 probably has the same problem, but I don't know how to fix it; there is no red zone and R2 is already used for something else. I'm going to leave it to someone interested in that target. Better still would be to rewrite the CR-saving code completely; spilling each CR subregister individually is horrible code. llvm-svn: 96015
* Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor ofDan Gohman2009-12-051-12/+0
| | | | | | | MachineBasicBlock::canFallThrough(), which is target-independent and more thorough. llvm-svn: 90634
* Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.Chris Lattner2009-08-221-2/+2
| | | | llvm-svn: 79763
* Move the getInlineAsmLength virtual method from TAI to TII, whereChris Lattner2009-08-021-1/+1
| | | | | | | | | | the only real caller (GetFunctionSizeInBytes) uses it. The custom ARM implementation of this is basically reimplementing an assembler poorly for negligible gain. It should be removed IMNSHO, but I'll leave that to ARMish folks to decide. llvm-svn: 77877
* Remove unused member functions.Eli Friedman2009-07-241-72/+0
| | | | llvm-svn: 76960
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-4/+4
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* Implement changes from Chris's feedback.Torok Edwin2009-07-081-8/+6
| | | | | | Finish converting lib/Target. llvm-svn: 75043
* Various small changes related to the Condition Register on PowerPC.Tilmann Scheller2009-07-031-16/+32
| | | | | | | | Don't spill to the CR save area when using the SVR4 ABI for now. Don't rely on constants assigned for registers to be in order (they aren't assigned in order). Make sure CR bits are mapped to the corresponding CR field. llvm-svn: 74767
* Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves ↵Evan Cheng2009-07-011-8/+28
| | | | | | the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. llvm-svn: 74580
* Change MachineInstrBuilder::addReg() to take a flag instead of a list ofBill Wendling2009-05-131-21/+43
| | | | | | | | | | | | booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
* PPC::B and PPC::BCC's target operand may be an immediate.Evan Cheng2009-05-081-0/+9
| | | | llvm-svn: 71282
* Factor out the code to add a MachineOperand to a MachineInstrBuilder.Dan Gohman2009-02-181-18/+4
| | | | llvm-svn: 64891
* Remove refs to non-DebugLoc version of BuildMI from PowerPC.Dale Johannesen2009-02-131-4/+6
| | | | llvm-svn: 64431
* Eliminate a couple of non-DebugLoc BuildMI variants.Dale Johannesen2009-02-121-16/+19
| | | | | | Modify callers. llvm-svn: 64409
* Move debug loc info along when the spiller creates new instructions.Bill Wendling2009-02-121-37/+46
| | | | llvm-svn: 64342
* Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nastyEvan Cheng2009-02-091-2/+4
| | | | | | | | suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. llvm-svn: 64124
* Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.Evan Cheng2009-02-061-10/+0
| | | | llvm-svn: 63938
* Change TargetInstrInfo::isMoveInstr to return source and destination ↵Evan Cheng2009-01-201-1/+5
| | | | | | sub-register indices as well. llvm-svn: 62600
* Split foldMemoryOperand into public non-virtual and protected virtualDan Gohman2008-12-031-4/+4
| | | | | | | parts, and add target-independent code to add/preserve MachineMemOperands. llvm-svn: 60488
* Add more const qualifiers. This fixes build breakage from r59540.Dan Gohman2008-11-181-2/+2
| | | | llvm-svn: 59542
* Const-ify several TargetInstrInfo methods.Dan Gohman2008-10-161-4/+4
| | | | llvm-svn: 57622
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-23/+23
| | | | | | isReg, etc., from isRegister, etc. llvm-svn: 57006
* Remove isImm(), isReg(), and friends, in favor of Dan Gohman2008-09-131-4/+4
| | | | | | | | | isImmediate(), isRegister(), and friends, to avoid confusion about having two different names with the same meaning. I'm not attached to the longer names, and would be ok with changing to the shorter names if others prefer it. llvm-svn: 56189
* Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy ↵Owen Anderson2008-08-261-5/+7
| | | | | | | | | requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
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