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* Implement asm support for a few PowerPC bookIII that are needed for assemblingRoman Divacky2013-09-121-0/+33
| | | | | | FreeBSD kernel. llvm-svn: 190618
* [PowerPC] Support "eieio" instructionUlrich Weigand2013-07-011-0/+6
| | | | | | | This adds support for the "eieio" instruction to the asm parser. llvm-svn: 185349
* [PowerPC] Add variants of "sync" instructionUlrich Weigand2013-07-011-1/+4
| | | | | | | This adds support for the "sync $L" instruction with operand, and provides aliases for "lwsync" and "ptesync". llvm-svn: 185344
* [PowerPC] Support generic conditional branches in asm parserUlrich Weigand2013-06-241-0/+14
| | | | | | | | | | | This adds instruction patterns to cover the generic forms of the conditional branch instructions. This allows the assembler to support the generic mnemonics. The compiler will still generate the various specific forms of the instruction that were already supported. llvm-svn: 184722
* Implement the PowerPC system call (sc) instruction.Bill Schmidt2013-05-141-0/+13
| | | | | | Instruction added at request of Roman Divacky. Tested via asm-parser. llvm-svn: 181821
* [PowerPC] Add some Book II instructions to AsmParserUlrich Weigand2013-05-031-0/+6
| | | | | | | | | | | | | This patch adds a couple of Book II instructions (isync, icbi) to the PowerPC assembler parser. These are needed when bootstrapping clang with the integrated assembler forced on, because they are used in inline asm statements in the code base. The test case adds the full list of Book II storage control instructions, including associated extended mnemonics. Again, those that are not yet supported as marked as FIXME. llvm-svn: 181052
* PowerPC: Fix encoding of rldimi and rldcl instructionsUlrich Weigand2013-04-261-0/+19
| | | | | | | | | | When testing the asm parser, I noticed wrong encodings for the above instructions (wrong operand name in rldimi, wrong form and sub-opcode for rldcl). Tests will be added together with the asm parser. llvm-svn: 180606
* Add a comment about the PPC Interpretation64Bit bitHal Finkel2013-04-121-0/+5
| | | | llvm-svn: 179391
* Add PPC instruction record forms and associated query functionsHal Finkel2013-04-121-1/+14
| | | | | | | | | | | | | | | | | | This is prep. work for the implementation of optimizeCompare. Many PPC instructions have 'record' forms (in almost all cases, this means that the RC bit is set) that cause the result of the instruction to be compared with zero, and the result of that comparison saved in a predefined condition register. In order to add the record forms of the instructions without too much copy-and-paste, the relevant functions have been refactored into multiclasses which define both the record and normal forms. Also, two TableGen-generated mapping functions have been added which allow querying the instruction code for the record form given the normal form (and vice versa). No functionality change intended. llvm-svn: 179356
* Generate PPC early conditional returnsHal Finkel2013-04-081-3/+3
| | | | | | | | | | | | | PowerPC has a conditional branch to the link register (return) instruction: BCLR. This should be used any time when we'd otherwise have a conditional branch to a return. This adds a small pass, PPCEarlyReturn, which runs just prior to the branch selection pass (and, importantly, after block placement) to generate these conditional returns when possible. It will also eliminate unconditional branches to returns (these happen rarely; most of the time these have already been tail duplicated by the time PPCEarlyReturn is invoked). This is a nice optimization for small functions that do not maintain a stack frame. llvm-svn: 179026
* PowerPC: Mark patterns as isCodeGenOnly.Ulrich Weigand2013-03-261-0/+1
| | | | | | | | | | | There remain a number of patterns that cannot (and should not) be handled by the asm parser, in particular all the Pseudo patterns. This commit marks those patterns as isCodeGenOnly. No change in generated code. llvm-svn: 178008
* PowerPC: Simplify FADD in round-to-zero mode.Ulrich Weigand2013-03-261-2/+1
| | | | | | | | | | | | | | | | | | | | | | | As part of the the sequence generated to implement long double -> int conversions, we need to perform an FADD in round-to-zero mode. This is problematical since the FPSCR is not at all modeled at the SelectionDAG level, and thus there is a risk of getting floating point instructions generated out of sequence with the instructions to modify FPSCR. The current code handles this by somewhat "special" patterns that in part have dummy operands, and/or duplicate existing instructions, making them awkward to handle in the asm parser. This commit changes this by leaving the "FADD in round-to-zero mode" as an atomic operation on the SelectionDAG level, and only split it up into real instructions at the MI level (via custom inserter). Since at *this* level the FPSCR *is* modeled (via the "RM" hard register), much of the "special" stuff can just go away, and the resulting patterns can be used by the asm parser. No significant change in generated code expected. llvm-svn: 178006
* PowerPC: Use CCBITRC operand for ISEL patterns.Ulrich Weigand2013-03-261-4/+2
| | | | | | | | | | | | This commit changes the ISEL patterns to use a CCBITRC operand instead of a "pred" operand. This matches the actual instruction text more directly, and simplifies use of ISEL with the asm parser. In addition, this change allows some simplification of handling the "pred" operand, as this is now only used by BCC. No change in generated code. llvm-svn: 178003
* Implement builtin_{setjmp/longjmp} on PPCHal Finkel2013-03-211-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This implements SJLJ lowering on PPC, making the Clang functions __builtin_{setjmp/longjmp} functional on PPC platforms. The implementation strategy is similar to that on X86, with the exception that a branch-and-link variant is used to get the right jump address. Credit goes to Bill Schmidt for suggesting the use of the unconditional bcl form (instead of the regular bl instruction) to limit return-address-cache pollution. Benchmarking the speed at -O3 of: static jmp_buf env_sigill; void foo() { __builtin_longjmp(env_sigill,1); } main() { ... for (int i = 0; i < c; ++i) { if (__builtin_setjmp(env_sigill)) { goto done; } else { foo(); } done:; } ... } vs. the same code using the libc setjmp/longjmp functions on a P7 shows that this builtin implementation is ~4x faster with Altivec enabled and ~7.25x faster with Altivec disabled. This comparison is somewhat unfair because the libc version must also save/restore the VSX registers which we don't yet support. llvm-svn: 177666
* Fix wrong PowerPC instruction encodings due toUlrich Weigand2012-11-131-4/+4
| | | | | | | | | operand field name mismatches in: - AForm_3 (fmul, fmuls) - XFXForm_5 (mtcrf) - XFLForm (mtfsf) llvm-svn: 167862
* Fix instruction encoding for "bd(n)z" on PowerPC,Ulrich Weigand2012-11-131-6/+7
| | | | | | by using a new instruction format BForm_1. llvm-svn: 167861
* Fix instruction encoding for "isel" on PowerPC,Ulrich Weigand2012-11-131-0/+20
| | | | | | using a new instruction format AForm_4. llvm-svn: 167860
* Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form ↵Hal Finkel2012-06-081-0/+6
| | | | | | | | | | CTR-based loop branching code. This pass is derived from the Hexagon HardwareLoops pass. The only significant enhancement over the Hexagon pass is that PPCCTRLoops will also attempt to delete the replaced add and compare operations if they are no longer otherwise used. Also, invalid preheader DebugLoc is not used. llvm-svn: 158204
* Fix dynamic linking on PPC64.Hal Finkel2012-03-311-0/+59
| | | | | | | | | | | | | | | | | | Dynamic linking on PPC64 has had problems since we had to move the top-down hazard-detection logic post-ra. For dynamic linking to work there needs to be a nop placed after every call. It turns out that it is really hard to guarantee that nothing will be placed in between the call (bl) and the nop during post-ra scheduling. Previous attempts at fixing this by placing logic inside the hazard detector only partially worked. This is now fixed in a different way: call+nop codegen-only instructions. As far as CodeGen is concerned the pair is now a single instruction and cannot be split. This solution works much better than previous attempts. The scoreboard hazard detector is also renamed to be more generic, there is currently no cpu-specific logic in it. llvm-svn: 153816
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-2/+2
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* split out an encoder for memri operands, allowing a relocation to be ploppedChris Lattner2010-11-151-2/+15
| | | | | | | | | | | | | | | | into the immediate field. This allows us to encode stuff like this: lbz r3, lo16(__ZL4init)(r4) ; globalopt.cpp:5 ; encoding: [0x88,0x64,A,A] ; fixup A - offset: 0, value: lo16(__ZL4init), kind: fixup_ppc_lo16 stw r3, lo16(__ZL1s)(r5) ; globalopt.cpp:6 ; encoding: [0x90,0x65,A,A] ; fixup A - offset: 0, value: lo16(__ZL1s), kind: fixup_ppc_lo16 With this, we should have a completely function MCCodeEmitter for PPC, wewt. llvm-svn: 119134
* add support for encoding the lo14 forms used for a few PPC64 addressingChris Lattner2010-11-151-4/+18
| | | | | | | | | modes. For example, we now get: ld r3, lo16(_G)(r3) ; encoding: [0xe8,0x63,A,0bAAAAAA00] ; fixup A - offset: 0, value: lo16(_G), kind: fixup_ppc_lo14 llvm-svn: 119133
* Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.Jakob Stoklund Olesen2010-04-051-3/+8
| | | | | | | | | | | | | | | | | | | When a target instruction wants to set target-specific flags, it should simply set bits in the TSFlags bit vector defined in the Instruction TableGen class. This works well because TableGen resolves member references late: class I : Instruction { AddrMode AM = AddrModeNone; let TSFlags{3-0} = AM.Value; } let AM = AddrMode4 in def ADD : I; TSFlags gets the expected bits from AddrMode4 in this example. llvm-svn: 100384
* Implement __sync_synchronize on ppc32. Patch by Gary Benson.Dale Johannesen2008-08-221-0/+11
| | | | llvm-svn: 55186
* Implement ISD::TRAP support on PPCNate Begeman2008-08-111-0/+11
| | | | llvm-svn: 54644
* no need to explicitly clear these fields.Chris Lattner2008-01-071-1/+0
| | | | llvm-svn: 45683
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Next PPC long double bits: ppcf128->i32 conversion.Dale Johannesen2007-10-101-0/+49
| | | | | | | Surprisingly complicated. Adds getTargetNode for 2 outputs, no inputs (missing). llvm-svn: 42822
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-130/+135
| | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
* Add XLForm_1_ext template, patch by Nicolas Geoffray.Chris Lattner2007-02-251-14/+24
| | | | llvm-svn: 34573
* fix another sradi encoding bug. This fixes Olden/health with the ppc64 jit.Chris Lattner2006-12-061-1/+1
| | | | llvm-svn: 32291
* fix the jit encoding of sradi, simplify the MDForm1 description.Chris Lattner2006-12-061-5/+5
| | | | llvm-svn: 32285
* Rewrite the branch selector to be correct in the face of large functions.Chris Lattner2006-11-181-16/+2
| | | | | | | | | | | | | | | The algorithm it used before wasn't 100% correct, we now use an iterative expansion model. This fixes assembler errors when compiling 403.gcc with tail merging enabled. Change the way the branch selector works overall: Now, the isel generates PPC::BCC instructions (as it used to) directly, and these BCC instructions are emitted to the output or jitted directly if branches don't need expansion. Only if branches need expansion are instructions rewritten and created. This should make branch select faster, and eliminates the Bxx instructions from the .td file. llvm-svn: 31837
* add encoding for BCC, after finally wrestling strange ppc/tblgen endiannessChris Lattner2006-11-171-0/+18
| | | | | | issues to the ground. llvm-svn: 31836
* Stop using isTwoAddress, switching to operand constraints instead.Chris Lattner2006-11-151-5/+0
| | | | | | | | Tell the codegen emitter that specific operands are not to be encoded, fixing JIT regressions w.r.t. pre-inc loads and stores (e.g. lwzu, which we generate even when general preinc loads are not enabled). llvm-svn: 31770
* implement preinc support for r+i loads on ppc64Chris Lattner2006-11-101-4/+0
| | | | llvm-svn: 31654
* dform 8/9 are identical to dform 1Chris Lattner2006-11-101-9/+0
| | | | llvm-svn: 31637
* fix encoding of BLRChris Lattner2006-11-071-2/+2
| | | | llvm-svn: 31485
* encode BLR predicate info for the JITChris Lattner2006-11-041-0/+13
| | | | llvm-svn: 31450
* Another fix in the rotate encodings, needed when the first two operands are notChris Lattner2006-07-131-1/+1
| | | | | | the same. llvm-svn: 29136
* Fix encoding of rotates, such as rldiclChris Lattner2006-07-121-3/+3
| | | | llvm-svn: 29128
* Add a pattern for i64 sra. Print 8-byte units with a space between the .quadChris Lattner2006-06-271-1/+2
| | | | | | and the data llvm-svn: 28934
* Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit fileChris Lattner2006-06-201-1/+0
| | | | llvm-svn: 28889
* remove unused flagChris Lattner2006-06-201-1/+0
| | | | llvm-svn: 28888
* Add PowerPC intrinsics to support dcbz[l]Chris Lattner2006-06-061-0/+17
| | | | llvm-svn: 28696
* Add all of the data stream intrinsics and instructions. wooChris Lattner2006-04-051-0/+22
| | | | llvm-svn: 27442
* Add m[tf]vscr instructions.Chris Lattner2006-04-051-0/+27
| | | | llvm-svn: 27421
* Fix the JIT encoding of VSELChris Lattner2006-03-271-0/+20
| | | | llvm-svn: 27160
* Fix the JIT encoding of VSPLTI*Chris Lattner2006-03-271-0/+15
| | | | llvm-svn: 27159
* Add all of the altivec comparison instructions. Add patterns for theChris Lattner2006-03-261-2/+3
| | | | | | non-predicate altivec compare intrinsics. llvm-svn: 27143
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