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path: root/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
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* implement proper PPC64 prolog/epilog codegen.Chris Lattner2006-11-111-0/+5
| | | | llvm-svn: 31684
* Mark operands as symbol lo instead of imm32 so that they print lo(x) aroundChris Lattner2006-11-111-5/+5
| | | | | | globals. llvm-svn: 31672
* implement preinc support for r+i loads on ppc64Chris Lattner2006-11-101-4/+38
| | | | llvm-svn: 31654
* Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.Evan Cheng2006-10-131-6/+6
| | | | llvm-svn: 30945
* Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.Evan Cheng2006-10-091-20/+20
| | | | llvm-svn: 30844
* Shift amounts are always 32-bits, even in 64-bit mode. This fixesChris Lattner2006-09-281-6/+6
| | | | | | CodeGen/PowerPC/2006-09-28-shift_64.ll llvm-svn: 30652
* Make the implicit def instructions look like other instrs.Chris Lattner2006-07-181-1/+1
| | | | llvm-svn: 29174
* Add missing PPC64 extload/truncstoresChris Lattner2006-07-141-7/+83
| | | | llvm-svn: 29140
* Don't match 64-bit bitfield inserts into rlwimi's. todo add rldimi. :)Chris Lattner2006-06-271-2/+0
| | | | llvm-svn: 28944
* Add a pattern for i64 sra. Print 8-byte units with a space between the .quadChris Lattner2006-06-271-2/+4
| | | | | | and the data llvm-svn: 28934
* Add 64-bit MTCTR so that indirect calls work.Chris Lattner2006-06-271-0/+4
| | | | llvm-svn: 28931
* Fix an incorrect store pattern. This fixes em3d.Chris Lattner2006-06-271-1/+1
| | | | llvm-svn: 28930
* Implement 64-bit undef, sub, shl/shr, srem/uremChris Lattner2006-06-271-3/+16
| | | | llvm-svn: 28929
* Add zextload from i32 -> i64, with this, perimeter works.Chris Lattner2006-06-271-0/+3
| | | | llvm-svn: 28926
* Rearrange compares, add ADDI8, add sext from 32-to-64 bit registerChris Lattner2006-06-261-8/+20
| | | | llvm-svn: 28920
* Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit fileChris Lattner2006-06-201-11/+22
| | | | llvm-svn: 28889
* add some logical opsChris Lattner2006-06-201-3/+28
| | | | llvm-svn: 28887
* Add some more immediate patterns. This allows us to compile:Chris Lattner2006-06-201-0/+30
| | | | | | | | | | | | | | | | | | | | void test6() { Y = 0xABCD0123BCDE4567; } into: _test6: lis r2, -21555 lis r3, ha16(_Y) ori r2, r2, 291 rldicr r2, r2, 32, 31 oris r2, r2, 48350 ori r2, r2, 17767 std r2, lo16(_Y)(r3) blr llvm-svn: 28885
* Instead of li/xoris use li/oris. Note that this doesn't work if bit 15 isChris Lattner2006-06-201-5/+5
| | | | | | set, so disable the pattern in that case. llvm-svn: 28884
* Add some 64-bit logical ops.Chris Lattner2006-06-201-8/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split imm16Shifted into a sext/zext form for 64-bit support. Add some patterns for immediate formation. For example, we now compile this: static unsigned long long Y; void test3() { Y = 0xF0F00F00; } into: _test3: li r2, 3840 lis r3, ha16(_Y) xoris r2, r2, 61680 std r2, lo16(_Y)(r3) blr GCC produces: _test3: li r0,0 lis r2,ha16(_Y) ori r0,r0,61680 sldi r0,r0,16 ori r0,r0,3840 std r0,lo16(_Y)(r2) blr llvm-svn: 28883
* Add some patterns for globals, so we can now compile this:Chris Lattner2006-06-201-1/+37
| | | | | | | | | | | | | | | | | | static unsigned long long X, Y; void test1() { X = Y; } into: _test1: lis r2, ha16(_Y) lis r3, ha16(_X) ld r2, lo16(_Y)(r2) std r2, lo16(_X)(r3) blr llvm-svn: 28879
* Add some patterns for ppc64Chris Lattner2006-06-201-13/+14
| | | | llvm-svn: 28866
* Upgrade some load/store instructions to use the proper addressing mode stuff.Chris Lattner2006-06-161-10/+10
| | | | llvm-svn: 28841
* fix some assumptions that pointers can only be 32-bits. With this, we canChris Lattner2006-06-161-19/+14
| | | | | | | | | | | | | | | | | | | | | now compile: static unsigned long X; void test1() { X = 0; } into: _test1: lis r2, ha16(_X) li r3, 0 stw r3, lo16(_X)(r2) blr Totally amazing :) llvm-svn: 28839
* Split 64-bit instructions out into a separate .td fileChris Lattner2006-06-161-0/+183
llvm-svn: 28838
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