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* Add PowerPC codegen for indirect branches.Bob Wilson2009-11-041-0/+4
| | | | llvm-svn: 86050
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-291-1/+1
| | | | | | | | bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. llvm-svn: 85517
* Model the carry bit on ppc32. Without this we couldDale Johannesen2009-09-181-17/+27
| | | | | | | move a SUBFC (etc.) below the SUBFE (etc.) that consumed the carry bit. Add missing ADDIC8, noticed along the way. llvm-svn: 82266
* Add support for the PowerPC 64-bit SVR4 ABI.Tilmann Scheller2009-08-151-0/+6
| | | | | | | | | | | | | | | | | The Link Register is volatile when using the 32-bit SVR4 ABI. Make it possible to use the 64-bit SVR4 ABI. Add non-volatile registers for the 64-bit SVR4 ABI. Make sure r2 is a reserved register when using the 64-bit SVR4 ABI. Update PPCFrameInfo for the 64-bit SVR4 ABI. Add FIXME for 64-bit Darwin PPC. Insert NOP instruction after direct function calls. Emit official procedure descriptors. Create TOC entries for GlobalAddress references. Spill 64-bit non-volatile registers to the correct slots. Only custom lower VAARG when using the 32-bit SVR4 ABI. Use simple VASTART lowering for the 64-bit SVR4 ABI. llvm-svn: 79091
* Refactor ABI code in the PowerPC backend.Tilmann Scheller2009-07-031-20/+20
| | | | | | | | | | | Make CalculateParameterAndLinkageAreaSize() Darwin-specific. Remove SVR4 specific code from LowerCALL_Darwin() and LowerFORMAL_ARGUMENTS_Darwin(). Rename MachoABI to DarwinABI for consistency. Rename ELF ABI to SVR4 ABI for consistency. Factor out common call return lowering between the Darwin and SVR4 ABI. Factor out common call lowering between the Darwin and SVR4 ABI. llvm-svn: 74766
* Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman2008-12-031-3/+3
| | | | llvm-svn: 60487
* Add a sanity-check to tablegen to catch the case where isSimpleLoadDan Gohman2008-12-031-0/+4
| | | | | | | | | is set but mayLoad is not set. Fix all the problems this turned up. Change code to not use isSimpleLoad instead of mayLoad unless it really wants isSimpleLoad. llvm-svn: 60459
* Add a RM pseudoreg for the rounding mode, whichDale Johannesen2008-10-291-21/+25
| | | | | | | | | | | | | | | | | allows ppcf128->int conversion to work with DeadInstructionElimination. This is now turned off but RM is harmless. It does not do a complete job of modeling the rounding mode. Revert marking MFCR as using all 7 CR subregisters; while correct, this caused the problem in PR 2964, plus the local RA crash noted in the comments. This was needed to make DeadInstructionElimination, but as we are not running that, it is backed out for now. Eventually it should go back in and the other problems fixed where they're broken. llvm-svn: 58391
* Mark defs and uses of CTR and LR correctly.Dale Johannesen2008-10-231-5/+14
| | | | | | | | Prevents DeadMachineInstructionElim from thinking things like MTCTR are dead (fixes massive testsuite breakage at -O0). llvm-svn: 58043
* Rename ConstantSDNode::getValue to getZExtValue, for consistencyDan Gohman2008-09-121-4/+4
| | | | | | | with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. llvm-svn: 56159
* Implement 32 & 64 bit versions of PPC atomicDale Johannesen2008-08-251-1/+22
| | | | | | binary primitives. llvm-svn: 55343
* Remove PPC-specific lowering for atomics; theDale Johannesen2008-08-251-8/+6
| | | | | | | | generic stuff works fine. Mark rewritten cmp-and-swap as not using CR1. llvm-svn: 55336
* Rewrite ppc code generated for __sync_{bool|val}_compare_and_swapDale Johannesen2008-08-221-4/+7
| | | | | | | so that lwarx and stwcx are always executed the same number of times. This is important for performance, I'm told. llvm-svn: 55163
* Implement llvm.atomic.cmp.swap.i32 on PPC. Patch by Gary Benson!Evan Cheng2008-07-121-16/+27
| | | | llvm-svn: 53505
* Tail call optimization improvements:Arnold Schwaighofer2008-04-301-1/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move platform independent code (lowering of possibly overwritten arguments, check for tail call optimization eligibility) from target X86ISelectionLowering.cpp to TargetLowering.h and SelectionDAGISel.cpp. Initial PowerPC tail call implementation: Support ppc32 implemented and tested (passes my tests and test-suite llvm-test). Support ppc64 implemented and half tested (passes my tests). On ppc tail call optimization is performed if caller and callee are fastcc call is a tail call (in tail call position, call followed by ret) no variable argument lists or byval arguments option -tailcallopt is enabled Supported: * non pic tail calls on linux/darwin * module-local tail calls on linux(PIC/GOT)/darwin(PIC) * inter-module tail calls on darwin(PIC) If constraints are not met a normal call will be emitted. A test checking the argument lowering behaviour on x86-64 was added. llvm-svn: 50477
* 64-bit atomic operations.Evan Cheng2008-04-191-0/+19
| | | | llvm-svn: 49949
* Replace all target specific implicit def instructions with a target ↵Evan Cheng2008-03-151-8/+0
| | | | | | independent one: TargetInstrInfo::IMPLICIT_DEF. llvm-svn: 48380
* Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl).Chris Lattner2008-03-071-3/+13
| | | | llvm-svn: 48027
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-3/+3
| | | | llvm-svn: 45667
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-061-1/+1
| | | | llvm-svn: 45656
* Change the 'isStore' inferrer to look for 'SDNPMayStore' Chris Lattner2008-01-061-5/+1
| | | | | | | | | | | instead of "ISD::STORE". This allows us to mark target-specific dag nodes as storing (such as ppc byteswap stores). This allows us to remove more explicit isStore flags from the .td files. Finally, add a warning for when a .td file contains an explicit isStore and tblgen is able to infer it. llvm-svn: 45654
* remove some isStore flags that are now inferred automatically.Chris Lattner2008-01-061-2/+2
| | | | llvm-svn: 45652
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Temporary solution: added a different set of BCTRL_Macho / BCTRL_ELF with ↵Evan Cheng2007-10-231-3/+9
| | | | | | right callee-saved defs set for ppc64. llvm-svn: 43248
* Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.Evan Cheng2007-09-111-2/+2
| | | | llvm-svn: 41863
* Fix for PR1613: added 64-bit rotate left PPC instructions and patterns.Evan Cheng2007-09-041-0/+10
| | | | llvm-svn: 41711
* Some out operands were incorrectly specified as input operands.Evan Cheng2007-08-011-9/+9
| | | | llvm-svn: 40697
* No more noResults.Evan Cheng2007-07-211-4/+4
| | | | llvm-svn: 40132
* Oops. These stores actually produce results.Evan Cheng2007-07-201-4/+4
| | | | llvm-svn: 40074
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-99/+103
| | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
* add support for 128-bit add/sub on ppc64Chris Lattner2007-05-171-0/+34
| | | | llvm-svn: 37158
* The PPC64 ELF ABI is "intended to use the same structure layout and calling ↵Nicolas Geoffray2007-04-031-2/+3
| | | | | | | | | convention rules as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/). Change all ELF tests to ELF32. llvm-svn: 35624
* The ELF ABI specifies F1-F8 registers as argument registers for double, notNicolas Geoffray2007-04-031-1/+1
| | | | | | F1-F10. This affects only ELF, not MachO. llvm-svn: 35622
* Fix CodeGen/PowerPC/2007-03-24-cntlzd.llChris Lattner2007-03-251-1/+4
| | | | llvm-svn: 35329
* Differentiate between the MachO and the ELF ABI the CALL instruction.Nicolas Geoffray2007-02-271-3/+2
| | | | llvm-svn: 34667
* one important bugfix: PPC32 didn't have both elf and macho support forChris Lattner2007-02-251-3/+3
| | | | | | | | | external symbols and global addresses. Add the missing ones. one important workaround: PPCISD::CALL is matched by both PPCcall_ELF and PPCcall_Macho, disable the _ELF patterns for now. llvm-svn: 34601
* implement support for the linux/ppc function call ABI. Patch byChris Lattner2007-02-251-8/+36
| | | | | | Nicolas Geoffray! llvm-svn: 34574
* Patterns no longer needed due to fix in the DAG combiner.Jim Laskey2006-12-151-4/+0
| | | | llvm-svn: 32612
* Not all test cases are created equal. This fix is needed.Jim Laskey2006-12-151-0/+4
| | | | llvm-svn: 32605
* Not needed. Misinterpreted error message from other bug (Missing load/storeJim Laskey2006-12-151-4/+0
| | | | | | relocations.) llvm-svn: 32604
* Provide 64-bit support for i64 sextload<i8>.Jim Laskey2006-12-151-0/+4
| | | | llvm-svn: 32600
* Reduce number of instructions to load 64-bit constants.Jim Laskey2006-12-121-42/+0
| | | | llvm-svn: 32481
* implement sextinreg i8->i64 and i16->i64Chris Lattner2006-12-061-0/+8
| | | | llvm-svn: 32293
* This is a general clean up of the PowerPC ABI. Address several problems andJim Laskey2006-11-161-0/+6
| | | | | | | | | bugs including making sure that the TOS links back to the previous frame, that the maximum call frame size is not included twice when using frame pointers, no longer growing the frame on calls, double storing of SP and a cleaner/faster dynamic alloca. llvm-svn: 31792
* fix a regression that I introduced. stdu should scale the offset by 4Chris Lattner2006-11-161-1/+1
| | | | | | before printing it. llvm-svn: 31791
* add ppc64 r+i stores with update.Chris Lattner2006-11-161-26/+59
| | | | llvm-svn: 31776
* Stop using isTwoAddress, switching to operand constraints instead.Chris Lattner2006-11-151-12/+17
| | | | | | | | Tell the codegen emitter that specific operands are not to be encoded, fixing JIT regressions w.r.t. pre-inc loads and stores (e.g. lwzu, which we generate even when general preinc loads are not enabled). llvm-svn: 31770
* fix ldu/stu jit encoding. Swith 64-bit preinc load instrs to use memriChris Lattner2006-11-151-16/+12
| | | | | | addrmodes. llvm-svn: 31757
* Fix the PPC regressions last nightChris Lattner2006-11-151-1/+1
| | | | llvm-svn: 31752
* Rework PPC64 calls. Now we have a LR8/CTR8 register which the PPC64 callsChris Lattner2006-11-141-1/+42
| | | | | | | | clobber. This allows LR8 to be save/restored correctly as a 64-bit quantity, instead of handling it as a 32-bit quantity. This unbreaks ppc64 codegen when the code is actually located above the 4G boundary. llvm-svn: 31734
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