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path: root/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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* [PowerPC] Rename DarwinDirective to CPUDirective (NFC)Kit Barton2019-11-251-7/+7
* [PowerPC] Fix VSX clobbers of CSR registersNemanja Ivanovic2019-11-251-0/+11
* [AIX][XCOFF] Generate undefined symbol in symbol table for external function ...jasonliu2019-11-251-2/+14
* [PowerPC] Implement the vector extend sign instruction pattern matchQingShan Zhang2019-11-221-0/+8
* [AIX] Lowering jump table, constant pool and block address in asmXiangling Liao2019-11-201-3/+3
* DAG: Add function context to isFMAFasterThanFMulAndFAddMatt Arsenault2019-11-191-1/+2
* [PowerPC] Option for enabling absolute jumptables with command lineNemanja Ivanovic2019-11-071-0/+5
* [AIX] Lowering CPI/JTI/BA to MIRXiangling Liao2019-10-301-6/+6
* [PowerPC] Emit scalar fp min/max instructionsNemanja Ivanovic2019-10-281-7/+35
* [AIX] Refactor AIX Call Lowering to use CCState. NFCI.Sean Fertile2019-10-281-94/+120
* [NFC] Replace 'isDarwin' with 'IsDarwin'Xiangling Liao2019-10-061-3/+3
* TLI: Remove DAG argument from getRegisterByNameMatt Arsenault2019-10-011-6/+6
* [Alignment][NFC] Remove unneeded llvm:: scoping on Align typesGuillaume Chatelet2019-09-271-8/+8
* Move classes into anonymous namespaces. NFC.Benjamin Kramer2019-09-221-1/+1
* [NFC][PowerPC] Refactor classifyGlobalReferenceJinsong Ji2019-09-201-8/+2
* [Alignment][NFC] Use Align::None instead of 1Guillaume Chatelet2019-09-181-4/+4
* [PowerPC] Exploit single instruction load-and-splat for word and doublewordNemanja Ivanovic2019-09-171-8/+89
* [SVE][MVT] Fixed-length vector MVT rangesGraham Hunter2019-09-171-2/+2
* [PowerPC] Cust lower fpext v2f32 to v2f64 from extract_subvector v4f32Nemanja Ivanovic2019-09-161-18/+41
* [PowerPC] Remove the SPE4RC register class and instead add f32 to the GPRC re...Craig Topper2019-09-121-3/+3
* [Alignment][NFC] Use llvm::Align for TargetLowering::getPrefLoopAlignmentGuillaume Chatelet2019-09-101-4/+4
* [Alignment] Use Align for TargetLowering::MinStackArgumentAlignmentGuillaume Chatelet2019-09-101-1/+1
* [SelectionDAG] Remove ISD::FP_ROUND_INREGCraig Topper2019-09-091-1/+0
* [Alignment][NFC] Use Align with TargetLowering::setPrefFunctionAlignmentGuillaume Chatelet2019-09-061-2/+2
* [Alignment][NFC] Use Align with TargetLowering::setPrefLoopAlignmentGuillaume Chatelet2019-09-061-1/+1
* [Alignment][NFC] Use Align with TargetLowering::setMinFunctionAlignmentGuillaume Chatelet2019-09-061-1/+1
* [LLVM][Alignment] Make functions using log of alignment explicitGuillaume Chatelet2019-09-051-6/+6
* [PowerPC] Expand v1i128 sminRoland Froese2019-08-231-4/+12
* [PowerPC] Add combined ELF ABI and 32/64 bit queries to the subtarget. [NFC]Sean Fertile2019-08-221-45/+47
* Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-151-42/+42
* [AIX] Add call lowering for parameters that could pass onto FPRsJason Liu2019-08-141-3/+21
* [AIX]Lowering global address for 32/64bit small/large code modelsXiangling Liao2019-08-131-18/+23
* [PowerPC] Fix ICE when truncating some vectorsQiu Chaofan2019-08-131-1/+3
* [LLVM][Alignment] Introduce Alignment TypeGuillaume Chatelet2019-08-051-4/+4
* recommit:[PowerPC] Eliminate loads/swap feeding swap/store for vector type by...Zi Xuan Wu2019-08-011-0/+72
* revert r367382 because buildbot failureZi Xuan Wu2019-07-311-71/+0
* [PowerPC] Eliminate loads/swap feeding swap/store for vector type by using bi...Zi Xuan Wu2019-07-311-0/+71
* [NFC][PowerPC]Change ADDIStocHA to ADDIStocHA8 to follow 64-bit naming conven...Jason Liu2019-07-221-1/+1
* PowerPC/SPE: Fix load/store handling for SPEJustin Hibbits2019-07-171-0/+23
* [NFC]Fix IR/MC depency issue for function descriptor SDAG implementationDavid Tenty2019-07-101-44/+35
* [PowerPC] Support constraint code "ww"Fangrui Song2019-07-041-4/+6
* [Codegen][X86][AArch64][ARM][PowerPC] Inc-of-add vs sub-of-not (PR42457)Roman Lebedev2019-07-031-0/+4
* [PowerPC][HTM] Fix disassembling buffer overflow for tabortdc and othersJinsong Ji2019-06-271-1/+10
* [PowerPC] Mark FCOPYSIGN legal for FP vectorsNemanja Ivanovic2019-06-261-0/+2
* CodeGen: Introduce a class for registersMatt Arsenault2019-06-241-52/+52
* PowerPC: Optimize SPE double parameter calling setupJustin Hibbits2019-06-171-38/+81
* [PowerPC] Set the innermost hot loop to align 32 bytesKang Zhang2019-06-151-0/+12
* [TargetLowering] Add MachineMemOperand::Flags to allowsMemoryAccess tests (PR...Simon Pilgrim2019-06-121-0/+1
* [CodeGen] Generic Hardware Loop SupportSam Parker2019-06-071-4/+4
* [PowerPC] Exploit the vector min/max instructionsNemanja Ivanovic2019-06-061-0/+18
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