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* fix PR3538 for PPCChris Lattner2009-02-121-4/+14
| | | | llvm-svn: 64383
* Eliminate remaining non-DebugLoc version of getTargetNode.Dale Johannesen2009-02-061-18/+18
| | | | llvm-svn: 63951
* Get rid of one more non-DebugLoc getNode andDale Johannesen2009-02-061-18/+20
| | | | | | | its corresponding getTargetNode. Lots of caller changes. llvm-svn: 63904
* Remove non-DebugLoc forms of CopyToReg and CopyFromReg.Dale Johannesen2009-02-041-18/+21
| | | | | | Adjust callers. llvm-svn: 63789
* Fix 80 col violations.Evan Cheng2009-01-191-2/+2
| | | | llvm-svn: 62518
* Handle ISD::DECLARE with PIC relocation model.Evan Cheng2009-01-191-4/+15
| | | | llvm-svn: 62516
* Fix PPC ISD::Declare isel and eliminate the need for ↵Evan Cheng2009-01-161-0/+20
| | | | | | PPCTargetLowering::LowerGlobalAddress to check if isVerifiedDebugInfoDesc() is true. Given the recent changes, it would falsely return true for a lot of GlobalAddressSDNode's. llvm-svn: 62373
* Generalize the HazardRecognizer interface so that it can be usedDan Gohman2009-01-151-1/+1
| | | | | | | to support MachineInstr-based scheduling in addition to SDNode-based scheduling. llvm-svn: 62284
* Move a few containers out of ScheduleDAGInstrs::BuildSchedGraphDan Gohman2009-01-151-1/+1
| | | | | | | | | | | and into the ScheduleDAGInstrs class, so that they don't get destructed and re-constructed for each block. This fixes a compile-time hot spot in the post-pass scheduler. To help facilitate this, tidy and do some minor reorganization in the scheduler constructor functions. llvm-svn: 62275
* Make FP tests requiring two compares work on PPC (PR 642).Dale Johannesen2008-11-071-16/+19
| | | | | | | | | | This is Chris' patch from the PR, modified to realize that SETUGT/SETULT occur legitimately with integers, plus two fixes in LegalizeDAG to pass a valid result type into LegalizeSetCC. The argument of TLI.getSetCCResultType is ignored on PPC, but I think I'm following usage elsewhere. llvm-svn: 58871
* Reintroduce a comment that was removed with the AddToISelQueueDan Gohman2008-11-051-0/+1
| | | | | | changes. llvm-svn: 58760
* Eliminate the ISel priority queue, which used the topological order for aDan Gohman2008-11-051-27/+1
| | | | | | | | | | | | | | | | | | | | | | | | priority function. Instead, just iterate over the AllNodes list, which is already in topological order. This eliminates a fair amount of bookkeeping, and speeds up the isel phase by about 15% on many testcases. The impact on most targets is that AddToISelQueue calls can be simply removed. In the x86 target, there are two additional notable changes. The rule-bending AND+SHIFT optimization in MatchAddress that creates new pre-isel nodes during isel is now a little more verbose, but more robust. Instead of either creating an invalid DAG or creating an invalid topological sort, as it has historically done, it can now just insert the new nodes into the node list at a position where they will be consistent with the topological ordering. Also, the address-matching code has logic that checked to see if a node was "already selected". However, when a node is selected, it has all its uses taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any further visits from MatchAddress. This code is now removed. llvm-svn: 58748
* Have TableGen emit setSubgraphColor calls under control of a -gen-debugDavid Greene2008-10-271-1/+1
| | | | | | | | flag. Then in a debugger developers can set breakpoints at these calls to see waht is about to be selected and what the resulting subgraph looks like. This really helps when debugging instruction selection. llvm-svn: 58278
* Trim #includes.Dan Gohman2008-10-161-2/+0
| | | | llvm-svn: 57649
* Avoid creating two TargetLowering objects for each target.Dan Gohman2008-10-031-2/+2
| | | | | | | | | | | | Instead, just create one, and make sure everything that needs it can access it. Previously most of the SelectionDAGISel subclasses all had their own TargetLowering object, which was redundant with the TargetLowering object in the TargetMachine subclasses, except on Sparc, where SparcTargetMachine didn't have a TargetLowering object. Change Sparc to work more like the other targets here. llvm-svn: 57016
* Rename ConstantSDNode::getValue to getZExtValue, for consistencyDan Gohman2008-09-121-8/+8
| | | | | | | with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. llvm-svn: 56159
* Clean up uses of TargetLowering::getTargetMachine.Dan Gohman2008-09-041-1/+1
| | | | llvm-svn: 55769
* fix a bunch of 80-col violationsGabor Greif2008-08-311-2/+4
| | | | llvm-svn: 55588
* erect abstraction boundaries for accessing SDValue members, rename Val -> ↵Gabor Greif2008-08-281-12/+12
| | | | | | Node to reflect semantics llvm-svn: 55504
* Move the point at which FastISel taps into the SelectionDAGISelDan Gohman2008-08-231-5/+4
| | | | | | | | | | | | | | | | | | process up to a higher level. This allows FastISel to leverage more of SelectionDAGISel's infastructure, such as updating Machine PHI nodes. Also, implement transitioning from SDISel back to FastISel in the middle of a block, so it's now possible to go back and forth. This allows FastISel to hand individual CallInsts and other complicated things off to SDISel to handle, while handling the rest of the block itself. To help support this, reorganize the SelectionDAG class so that it is allocated once and reused throughout a function, instead of being completely reallocated for each block. llvm-svn: 55219
* Simplify SelectRoot's interface, and factor out some common codeDan Gohman2008-08-211-1/+1
| | | | | | from all targets. llvm-svn: 55124
* Rename SDOperand to SDValue.Dan Gohman2008-07-271-108/+108
| | | | llvm-svn: 54128
* Add a new function, ReplaceAllUsesOfValuesWith, which handles bulkDan Gohman2008-07-171-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | replacement of multiple values. This is slightly more efficient than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically could be optimized even further. However, an important property of this new function is that it handles the case where the source value set and destination value set overlap. This makes it feasible for isel to use SelectNodeTo in many very common cases, which is advantageous because SelectNodeTo avoids a temporary node and it doesn't require CSEMap updates for users of values that don't change position. Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to handle operand lists more efficiently, and to correctly handle a number of corner cases to which its new wider use exposes it. This commit also includes a change to the encoding of post-isel opcodes in SDNodes; now instead of being sandwiched between the target-independent pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel opcodes are now represented as negative values. This makes it possible to test if an opcode is pre-isel or post-isel without having to know the size of the current target's post-isel instruction set. These changes speed up llc overall by 3% and reduce memory usage by 10% on the InstructionCombining.cpp testcase with -fast and -regalloc=local. llvm-svn: 53728
* Add explicit keywords.Dan Gohman2008-07-071-1/+1
| | | | llvm-svn: 53179
* Split scheduling from instruction selection.Evan Cheng2008-06-301-7/+4
| | | | llvm-svn: 52923
* Wrap MVT::ValueType in a struct to get type safetyDuncan Sands2008-06-061-3/+3
| | | | | | | | | | | | | | | | and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
* Convert the last remaining users of the non-APInt form ofDan Gohman2008-02-271-5/+5
| | | | | | | ComputeMaskedBits to use the APInt form, and remove the non-APInt form. llvm-svn: 47654
* Remove bunch of gcc 4.3-related warnings from TargetAnton Korobeynikov2008-02-201-2/+2
| | | | llvm-svn: 47369
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-1/+1
| | | | llvm-svn: 46930
* Dwarf requires variable entries to be in the source order. Right now, since ↵Evan Cheng2008-02-041-1/+0
| | | | | | we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead. llvm-svn: 46724
* SDIsel processes llvm.dbg.declare by recording the variable debug ↵Evan Cheng2008-02-021-0/+1
| | | | | | | | | information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes. For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time. llvm-svn: 46659
* Factor the addressing mode and the load/store VT out of LoadSDNodeDan Gohman2008-01-301-1/+1
| | | | | | | | and StoreSDNode into their common base class LSBaseSDNode. Member functions getLoadedVT and getStoredVT are replaced with the common getMemoryVT to simplify code that will handle both loads and stores. llvm-svn: 46538
* Finally implement correct ordered comparisons for PPC, even thoughChris Lattner2008-01-081-24/+43
| | | | | | | | the code generated is not wonderful. This turns a miscompilation into a code quality bug (noted in the ppc readme). This fixes PR642, which is over 2 years old (!). Nate, please review this. llvm-svn: 45742
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-2/+2
| | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
* Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptorChris Lattner2008-01-071-1/+1
| | | | llvm-svn: 45680
* Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflectsChris Lattner2008-01-071-2/+3
| | | | | | | | | | | | | | | that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. llvm-svn: 45674
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-9/+7
| | | | | | | | | | | | | | that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Temporary solution: added a different set of BCTRL_Macho / BCTRL_ELF with ↵Evan Cheng2007-10-231-3/+5
| | | | | | right callee-saved defs set for ppc64. llvm-svn: 43248
* Prevent PPC::BCC first operand, the PRED number, from being isel'd into a LI ↵Evan Cheng2007-06-291-1/+4
| | | | | | instruction. llvm-svn: 37790
* Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits fromDan Gohman2007-06-221-2/+2
| | | | | | | | | TargetLowering to SelectionDAG so that they have more convenient access to the current DAG, in preparation for the ValueType routines being changed from standalone functions to members of SelectionDAG for the pre-legalize vector type changes. llvm-svn: 37704
* Fix a bug which caused us to never be able to use signed comparisons forChris Lattner2007-04-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | equality comparisons of a constant. This allows us to codegen the 'sintzero' loop in PR1288 as: LBB1_1: ;cond_next li r4, 0 addi r2, r2, 1 stw r4, 0(r3) addi r3, r3, 4 cmpwi cr0, r2, -1 bne cr0, LBB1_1 ;cond_next instead of: LBB1_1: ;cond_next addi r2, r2, 1 li r4, 0 xoris r5, r2, 65535 stw r4, 0(r3) addi r3, r3, 4 cmplwi cr0, r5, 65535 bne cr0, LBB1_1 ;cond_next This implements CodeGen/PowerPC/compare-simm.ll, and also cuts 74 instructions out of kc++. llvm-svn: 35590
* eliminate static ctors for Statistic objects.Chris Lattner2006-12-191-3/+1
| | | | llvm-svn: 32703
* Reduce number of instructions to load 64-bit constants.Jim Laskey2006-12-121-0/+75
| | | | llvm-svn: 32481
* What should be the last unnecessary <iostream>s in the library.Bill Wendling2006-12-071-1/+0
| | | | llvm-svn: 32333
* Detemplatize the Statistic class. The only type it is instantiated withChris Lattner2006-12-061-1/+1
| | | | | | is 'unsigned'. llvm-svn: 32279
* Change MachineInstr ctor's to take a TargetInstrDescriptor reference insteadEvan Cheng2006-11-271-9/+10
| | | | | | of opcode and number of operands. llvm-svn: 31947
* convert PPC::BCC to use the 'pred' operand instead of separate predicateChris Lattner2006-11-171-1/+11
| | | | | | | | value and CR reg #. This requires swapping the order of these everywhere that touches BCC and requires us to write custom matching logic for PPCcondbranch :( llvm-svn: 31835
* rename PPC::COND_BRANCH to PPC::BCCChris Lattner2006-11-171-1/+1
| | | | llvm-svn: 31834
* start using PPC predicates more consistently.Chris Lattner2006-11-171-14/+12
| | | | llvm-svn: 31833
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