bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
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*	LVXL and STVXL are also a load and store resp.	Bill Wendling	2007-09-05	1	-0/+2
\| \| \| \|	llvm-svn: 41733
*	Skeleton of post-RA scheduler; doesn't do anything yet.	Dale Johannesen	2007-07-13	1	-1/+1
\| \| \| \| \| \| \|	Change name of -sched option and DEBUG_TYPE to pre-RA-sched; adjust testcases. llvm-svn: 39816
*	Fix parenthesis for BCTRL_{ELF\|Macho} test.	Nicolas Geoffray	2007-02-27	1	-1/+1
\| \| \| \|	llvm-svn: 34668
*	implement support for the linux/ppc function call ABI. Patch by	Chris Lattner	2007-02-25	1	-1/+1
\| \| \| \| \| \|	Nicolas Geoffray! llvm-svn: 34574
*	What should be the last unnecessary <iostream>s in the library.	Bill Wendling	2006-12-07	1	-3/+1
\| \| \| \|	llvm-svn: 32333
*	add ppc64 r+i stores with update.	Chris Lattner	2006-11-16	1	-14/+13
\| \| \| \|	llvm-svn: 31776
*	Switch loads over to use memri as the operand instead of a reg/imm operand	Chris Lattner	2006-11-15	1	-6/+5
\| \| \| \| \| \| \| \|	pair for cleanliness. Add instructions for PPC32 preinc-stores with commented out patterns. More improvement is needed to enable the patterns, but we're getting close. llvm-svn: 31749
*	teach the g5 hazard recognizer about update loads. This fixes	Chris Lattner	2006-11-13	1	-11/+10
\| \| \| \| \| \|	Ptrdist/anagram among others. llvm-svn: 31708
*	Add missing PPC64 extload/truncstores	Chris Lattner	2006-07-14	1	-2/+16
\| \| \| \|	llvm-svn: 29140
*	Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswaps	Chris Lattner	2006-07-10	1	-0/+4
\| \| \| \| \| \|	into i16/i32 load/stores. llvm-svn: 29089
*	When possible, custom lower 32-bit SINT_TO_FP to this:	Chris Lattner	2006-03-22	1	-1/+2
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	_foo2: extsw r2, r3 std r2, -8(r1) lfd f0, -8(r1) fcfid f0, f0 frsp f1, f0 blr instead of this: _foo2: lis r2, ha16(LCPI2_0) lis r4, 17200 xoris r3, r3, 32768 stw r3, -4(r1) stw r4, -8(r1) lfs f0, lo16(LCPI2_0)(r2) lfd f1, -8(r1) fsub f0, f1, f0 frsp f1, f0 blr This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s with llcbeta (16.7% and 38.1% respectively). llvm-svn: 26943
*	Fix a couple of bugs that broke the alpha tester build	Chris Lattner	2006-03-13	1	-2/+2
\| \| \| \|	llvm-svn: 26722
*	Handle cracked instructions in dispatch group formation.	Chris Lattner	2006-03-13	1	-14/+27
\| \| \| \|	llvm-svn: 26721
*	Several big changes:	Chris Lattner	2006-03-12	1	-137/+145
\| \| \| \| \| \| \| \| \| \| \|	1. Use flags on the instructions in the .td file to indicate the PPC970 unit type instead of a table in the .cpp file. Much cleaner. 2. Change the hazard recognizer to build d-groups according to the actual algorithm used, not my flawed understanding of it. 3. Model "must be in the first slot" and "must be the only instr in a group" accurately. llvm-svn: 26719
*	blr is a branch too	Chris Lattner	2006-03-11	1	-0/+1
\| \| \| \|	llvm-svn: 26710
*	Change the interface for getting a target HazardRecognizer to be more clean.	Chris Lattner	2006-03-08	1	-6/+4
\| \| \| \|	llvm-svn: 26608
*	add another missing store.	Chris Lattner	2006-03-07	1	-0/+2
\| \| \| \|	llvm-svn: 26595
*	add a couple more load/store instrs, add a newline to the end of file.	Chris Lattner	2006-03-07	1	-1/+15
\| \| \| \|	llvm-svn: 26594
*	This kinda sorta implements "things that have to lead a dispatch group".	Nate Begeman	2006-03-07	1	-16/+40
\| \| \| \|	llvm-svn: 26591
*	add some new instructions to the classifier. With this, we correctly insert	Chris Lattner	2006-03-07	1	-0/+11
\| \| \| \| \| \|	a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%). llvm-svn: 26590
*	add some comments that describe what we model	Chris Lattner	2006-03-07	1	-3/+18
\| \| \| \|	llvm-svn: 26588
*	Implement a very very simple hazard recognizer for LSU rejects and ctr set/read	Chris Lattner	2006-03-07	1	-0/+203
	flushes llvm-svn: 26587