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path: root/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
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* Rename SDOperand to SDValue.Dan Gohman2008-07-271-1/+1
| | | | llvm-svn: 54128
* Add a new function, ReplaceAllUsesOfValuesWith, which handles bulkDan Gohman2008-07-171-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | replacement of multiple values. This is slightly more efficient than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically could be optimized even further. However, an important property of this new function is that it handles the case where the source value set and destination value set overlap. This makes it feasible for isel to use SelectNodeTo in many very common cases, which is advantageous because SelectNodeTo avoids a temporary node and it doesn't require CSEMap updates for users of values that don't change position. Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to handle operand lists more efficiently, and to correctly handle a number of corner cases to which its new wider use exposes it. This commit also includes a change to the encoding of post-isel opcodes in SDNodes; now instead of being sandwiched between the target-independent pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel opcodes are now represented as negative values. This makes it possible to test if an opcode is pre-isel or post-isel without having to know the size of the current target's post-isel instruction set. These changes speed up llc overall by 3% and reduce memory usage by 10% on the InstructionCombining.cpp testcase with -fast and -regalloc=local. llvm-svn: 53728
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-1/+1
| | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
* use predicate.Chris Lattner2008-01-071-1/+1
| | | | llvm-svn: 45691
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-1/+1
| | | | llvm-svn: 45667
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-061-1/+1
| | | | llvm-svn: 45656
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* LVXL and STVXL are also a load and store resp.Bill Wendling2007-09-051-0/+2
| | | | llvm-svn: 41733
* Skeleton of post-RA scheduler; doesn't do anything yet.Dale Johannesen2007-07-131-1/+1
| | | | | | | Change name of -sched option and DEBUG_TYPE to pre-RA-sched; adjust testcases. llvm-svn: 39816
* Fix parenthesis for BCTRL_{ELF|Macho} test.Nicolas Geoffray2007-02-271-1/+1
| | | | llvm-svn: 34668
* implement support for the linux/ppc function call ABI. Patch byChris Lattner2007-02-251-1/+1
| | | | | | Nicolas Geoffray! llvm-svn: 34574
* What should be the last unnecessary <iostream>s in the library.Bill Wendling2006-12-071-3/+1
| | | | llvm-svn: 32333
* add ppc64 r+i stores with update.Chris Lattner2006-11-161-14/+13
| | | | llvm-svn: 31776
* Switch loads over to use memri as the operand instead of a reg/imm operandChris Lattner2006-11-151-6/+5
| | | | | | | | pair for cleanliness. Add instructions for PPC32 preinc-stores with commented out patterns. More improvement is needed to enable the patterns, but we're getting close. llvm-svn: 31749
* teach the g5 hazard recognizer about update loads. This fixesChris Lattner2006-11-131-11/+10
| | | | | | Ptrdist/anagram among others. llvm-svn: 31708
* Add missing PPC64 extload/truncstoresChris Lattner2006-07-141-2/+16
| | | | llvm-svn: 29140
* Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswapsChris Lattner2006-07-101-0/+4
| | | | | | into i16/i32 load/stores. llvm-svn: 29089
* When possible, custom lower 32-bit SINT_TO_FP to this:Chris Lattner2006-03-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | _foo2: extsw r2, r3 std r2, -8(r1) lfd f0, -8(r1) fcfid f0, f0 frsp f1, f0 blr instead of this: _foo2: lis r2, ha16(LCPI2_0) lis r4, 17200 xoris r3, r3, 32768 stw r3, -4(r1) stw r4, -8(r1) lfs f0, lo16(LCPI2_0)(r2) lfd f1, -8(r1) fsub f0, f1, f0 frsp f1, f0 blr This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s with llcbeta (16.7% and 38.1% respectively). llvm-svn: 26943
* Fix a couple of bugs that broke the alpha tester buildChris Lattner2006-03-131-2/+2
| | | | llvm-svn: 26722
* Handle cracked instructions in dispatch group formation.Chris Lattner2006-03-131-14/+27
| | | | llvm-svn: 26721
* Several big changes:Chris Lattner2006-03-121-137/+145
| | | | | | | | | | | 1. Use flags on the instructions in the .td file to indicate the PPC970 unit type instead of a table in the .cpp file. Much cleaner. 2. Change the hazard recognizer to build d-groups according to the actual algorithm used, not my flawed understanding of it. 3. Model "must be in the first slot" and "must be the only instr in a group" accurately. llvm-svn: 26719
* blr is a branch tooChris Lattner2006-03-111-0/+1
| | | | llvm-svn: 26710
* Change the interface for getting a target HazardRecognizer to be more clean.Chris Lattner2006-03-081-6/+4
| | | | llvm-svn: 26608
* add another missing store.Chris Lattner2006-03-071-0/+2
| | | | llvm-svn: 26595
* add a couple more load/store instrs, add a newline to the end of file.Chris Lattner2006-03-071-1/+15
| | | | llvm-svn: 26594
* This kinda sorta implements "things that have to lead a dispatch group".Nate Begeman2006-03-071-16/+40
| | | | llvm-svn: 26591
* add some new instructions to the classifier. With this, we correctly insertChris Lattner2006-03-071-0/+11
| | | | | | a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%). llvm-svn: 26590
* add some comments that describe what we modelChris Lattner2006-03-071-3/+18
| | | | llvm-svn: 26588
* Implement a very very simple hazard recognizer for LSU rejects and ctr set/readChris Lattner2006-03-071-0/+203
flushes llvm-svn: 26587
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