| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add ori reg, reg, 0 as a move instruction. This can be generated from | Nate Begeman | 2004-10-07 | 1 | -0/+11 |
| | | | | | | | | | | | | | | | | | | loading a 32bit constant into a register whose low halfword is all zeroes. We now omit the ori after the lis for the following C code: int bar(int y) { return y * 0x00F0000; } _bar: .LBB_bar_0: ; entry ; IMPLICIT_DEF lis r2, 15 mullw r3, r3, r2 blr llvm-svn: 16825 | ||||
| * | PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC* | Misha Brukman | 2004-08-17 | 1 | -0/+59 |
| llvm-svn: 15850 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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