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path: root/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
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* Implement bitfield clearsNate Begeman2005-04-121-11/+31
| | | | | | Implement divide by negative power of two llvm-svn: 21240
* Add recording variants of ISD::AND and ISD::OR. This kills almost 1000Nate Begeman2005-04-111-10/+43
| | | | | | (1.5%) instructions in 186.crafty llvm-svn: 21222
* Fix another fixme: factor out the constant fp generation code.Nate Begeman2005-04-101-17/+2
| | | | llvm-svn: 21207
* Fix 64 bit argument loading that straddles the args in regs / args on stackNate Begeman2005-04-101-7/+15
| | | | | | boundary. llvm-svn: 21206
* Make sure that BRCOND branches can be converted into long branches too.Nate Begeman2005-04-101-1/+3
| | | | llvm-svn: 21198
* Don't hand ISD::CALL nodes off to SelectExprFP. This fixes siod.Nate Begeman2005-04-101-1/+2
| | | | llvm-svn: 21197
* fix ISD::BRCONDTWOWAY codegen to not deference the end() iteratorNate Begeman2005-04-091-1/+1
| | | | llvm-svn: 21193
* do not set the root to null if an argument is deadChris Lattner2005-04-091-1/+2
| | | | llvm-svn: 21188
* Add rlwnm instruction for variable rotateNate Begeman2005-04-091-28/+76
| | | | | | | | Generate rotate left/right immediate Generate code for brcondtwoway Use new livein/liveout functionality llvm-svn: 21187
* Optimize FSEL a bit for fneg arguments. This fixes the recently added testNate Begeman2005-04-091-11/+12
| | | | | | | | | | | | | | | | | | | | case so that we emit _test_fneg_sel: .LBB_test_fneg_sel_0: ; fsel f1, f1, f3, f2 blr instead of: _test_fneg_sel: .LBB_test_fneg_sel_0: ; fneg f0, f1 fneg f0, f0 fsel f1, f0, f3, f2 blr llvm-svn: 21177
* This target does not yet support ISD::BRCONDTWOWAYChris Lattner2005-04-091-0/+1
| | | | llvm-svn: 21163
* 64b: Expand S/UREMNate Begeman2005-04-091-7/+27
| | | | | | | | | 32b: No longer pattern match fneg(fsub(fmul)) as fnmsub Pattern match fsub a, mul(b, c) as fnmsub Pattern match fadd a, mul(b, c) as fmadd Those changes speed up hydro2d by 2.5%, distray by 6%, and scimark by 8% llvm-svn: 21161
* Optimized code sequences for setcc reg, 0Nate Begeman2005-04-071-4/+77
| | | | | | Optimized code sequence for (a < 0) ? b : 0 llvm-svn: 21150
* PowerPC zero extends setcc resultsChris Lattner2005-04-071-0/+1
| | | | llvm-svn: 21147
* Pattern match bitfield insert, which helps shift long by immediate, amongNate Begeman2005-04-061-15/+152
| | | | | | other things. llvm-svn: 21127
* Fixed version of optimized integer divide is now fixed. Calculate theNate Begeman2005-04-061-13/+9
| | | | | | | quotient, not the remainder. Also, make sure to remove the old div operand from the ExprMap and let SelectExpr insert the new one. llvm-svn: 21111
* Turn off the div -> mul optimization until it works correctly 100% of theNate Begeman2005-04-061-5/+5
| | | | | | time. llvm-svn: 21105
* Add support for MULHS and MULHU nodesNate Begeman2005-04-061-20/+192
| | | | | | | | Have LegalizeDAG handle SREM and UREM for us Codegen SDIV and UDIV by constant as a multiply by magic constant instead of integer divide, which is very slow. llvm-svn: 21104
* Back out the previous change to SelectBranchCC, since there are cases itNate Begeman2005-04-051-4/+11
| | | | | | could miscompile. A correct solution will be found in the near future. llvm-svn: 21095
* Rename canUseAsImmediateForOpcode to getImmediateForOpcode to betterNate Begeman2005-04-051-17/+23
| | | | | | | | | indicate that it is not a boolean function. Properly emit the pseudo instruction for conditional branch, so that we can fix up conditional branches whose displacements are too large. Reserve the right amount of opcode space for said pseudo instructions. llvm-svn: 21094
* Implement SDIV by power of 2 as srawi/addze rather than load imm, divwNate Begeman2005-04-051-0/+24
| | | | llvm-svn: 21091
* Pattern match fp mul-add, mul-sub, neg-mul-add, and neg-mul-subNate Begeman2005-04-041-4/+56
| | | | llvm-svn: 21090
* Make sure that arg regs used by the call instruction are marked as such, soNate Begeman2005-04-041-15/+25
| | | | | | | that regalloc doesn't cleverly reuse early arg regs loading later arg regs. This fixes almost all outstanding failures in the pattern isel. llvm-svn: 21086
* i1 loads should also be from the low byte of the argument word.Nate Begeman2005-04-041-1/+1
| | | | llvm-svn: 21077
* Fix i64 return, fix CopyFromRegNate Begeman2005-04-041-3/+14
| | | | llvm-svn: 21076
* Full varargs support. All of UnitTests now passesNate Begeman2005-04-031-5/+15
| | | | llvm-svn: 21070
* Pass the correct value for the chain to the storeNate Begeman2005-04-031-3/+2
| | | | llvm-svn: 21066
* Fix SHL_PARTSNate Begeman2005-04-031-2/+10
| | | | | | Start implementation of integer varargs llvm-svn: 21065
* Keeping up with the Joneses.Nate Begeman2005-04-031-10/+51
| | | | | | Implement not, nor, nand, and eqv llvm-svn: 21060
* Set shift amount to ExtendNate Begeman2005-04-021-24/+101
| | | | | | | | Implement ISD::FABS and ISD::FNEG nodes Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions llvm-svn: 21018
* This target doesn't support fabs/fneg yet.Chris Lattner2005-04-021-0/+4
| | | | llvm-svn: 21010
* Fix i64 returnsNate Begeman2005-04-021-8/+9
| | | | | | Generate PowerPC 'subfic' instruction when appropriate llvm-svn: 20995
* Add ISD::UNDEF nodeNate Begeman2005-04-011-41/+67
| | | | | | | | | Teach the SelectionDAG code how to expand and promote it Have PPC32 LowerCallTo generate ISD::UNDEF for int arg regs used up by fp arguments, but not shadowing their value. This allows us to do the right thing with both fixed and vararg floating point arguments. llvm-svn: 20988
* Fix Olden/bh, CR0 was being set in the wrong orderNate Begeman2005-04-011-5/+3
| | | | | | | LowerCallTo and ISD::CALL are going to need to be modified, regs are being set in the wrong order. llvm-svn: 20981
* Also apply Chris's fix to FP select and SETCCNate Begeman2005-04-011-6/+8
| | | | llvm-svn: 20979
* Move the selection of the arms of the select operation up to the conditionalChris Lattner2005-04-011-2/+3
| | | | | | part to make sure we get the side effects and to avoid confusing the CFG. llvm-svn: 20977
* Fix stores to global addressesNate Begeman2005-04-011-7/+3
| | | | | | Fix calls with no arguments llvm-svn: 20975
* Support indexed loads and stores. This drops Shootout/matrix time fromNate Begeman2005-04-011-11/+40
| | | | | | | 18.8 to 14.8 seconds. The Pattern ISel is now often faster than the Simple ISel, esp. on memory intensive code. llvm-svn: 20973
* Implement FP_TO_SINT and FP_TO_UINTNate Begeman2005-04-011-11/+86
| | | | llvm-svn: 20972
* Add support for adding 0.0 and -0.0 to the constant pool, since we lie andNate Begeman2005-04-011-3/+11
| | | | | | say that we support them, for the purposes of generating fsel instructions. llvm-svn: 20970
* Factor out common code, support FP comparison in folded SetCCNate Begeman2005-04-011-84/+40
| | | | llvm-svn: 20969
* fsel generation for f32 and f64 selectNate Begeman2005-03-311-35/+181
| | | | | | | | | | generate compare immediate for integer compare with constant fold setcc into branch fold setcc into select Code generation quality for Shootout is now on par with the Simple ISel llvm-svn: 20968
* Pass the correct values to the chain argument for node construction duringNate Begeman2005-03-311-6/+14
| | | | | | | | LowerCallTo. Handle ISD::ADD in SelectAddr, allowing us to have nonzero immediates for loads and stores, amazing! llvm-svn: 20946
* Rewrite LowerCallTo and Select(ISD::CALL) to properly handle float varargsNate Begeman2005-03-311-135/+82
| | | | | | | | | | | | Tell the SelectionDAG ISel to expand SEXTLOAD of i1 and i8, rather than complicate the code in ISD::SEXTLOAD to do it by hand Combine the FP and Int ISD::LOAD codegen Generate better code for constant pool loads As a result, all of Shootout, and likely many other programs are now working. llvm-svn: 20945
* Fix calls whose arguments fit entirely in registers to not break the Chain.Nate Begeman2005-03-301-4/+51
| | | | | | | Implement SINT_TO_FP and UINT_TO_FP Remove some dead code from the simple ISel llvm-svn: 20944
* Fix frame index code to generate legal PowerPC instructions. About half ofNate Begeman2005-03-301-9/+7
| | | | | | Shootout now works. llvm-svn: 20940
* Fix external symbol printing in the AsmPrinter. Tell the ISel that weNate Begeman2005-03-301-0/+6
| | | | | | | don't support things like memcpy directly. This allows a handful of the Shootout programs to work, yay! llvm-svn: 20939
* Fix BranchCC (it's still dumb), and implement FP select (also dumb)Nate Begeman2005-03-291-4/+49
| | | | llvm-svn: 20935
* Implement integer select and i1 sign extendNate Begeman2005-03-291-2/+49
| | | | llvm-svn: 20934
* Implement SetCC, fix ZERO_EXTEND_INREGNate Begeman2005-03-291-6/+73
| | | | llvm-svn: 20933
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