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path: root/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
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* Pass in Calling Convention to use into LowerCallToChris Lattner2005-05-121-1/+2
* These targets don't like setccChris Lattner2005-05-121-0/+3
* Necessary changes to codegen cttz efficiently on PowerPCNate Begeman2005-05-111-6/+28
* fold and (shl X, C1), C2 -> rlwinm when possible. Many other cases are possi...Chris Lattner2005-05-091-1/+20
* fix typoAndrew Lenharth2005-05-041-1/+1
* Implement count leading zeros (ctlz), count trailing zeros (cttz), and countAndrew Lenharth2005-05-031-0/+5
* This target doesn't support the FSIN/FCOS/FSQRT nodes yetChris Lattner2005-04-301-0/+8
* Implement Value* tracking for loads and stores in the selection DAG. This en...Andrew Lenharth2005-04-271-11/+11
* Convert tabs to spacesMisha Brukman2005-04-221-3/+4
* Remove trailing whitespaceMisha Brukman2005-04-211-135/+135
* Match another form of eqvChris Lattner2005-04-211-1/+6
* Next round of PPC CR optimizations. For the following code:Nate Begeman2005-04-181-62/+95
* Change codegen for setcc to read the bit directly out of the conditionNate Begeman2005-04-181-42/+31
* Make pattern isel default for ppcNate Begeman2005-04-151-3/+2
* Implement multi-way branches through logical ops on condition registers.Nate Begeman2005-04-141-2/+68
* Start allocating condition registers. Almost all explicit uses of CR0 areNate Begeman2005-04-131-23/+26
* Implement the fold shift X, zext(Y) -> shift X, Y at the target level,Nate Begeman2005-04-131-6/+22
* Disbale the broken fold of shift + sz[ext] for nowNate Begeman2005-04-131-19/+0
* remove one more occurance of this that snuck inChris Lattner2005-04-131-1/+1
* Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emitChris Lattner2005-04-131-13/+0
* Fold shift by size larger than type size to undefNate Begeman2005-04-121-1/+0
* Implement setcc op, -1 sequencesNate Begeman2005-04-121-22/+41
* Implement bitfield clearsNate Begeman2005-04-121-11/+31
* Add recording variants of ISD::AND and ISD::OR. This kills almost 1000Nate Begeman2005-04-111-10/+43
* Fix another fixme: factor out the constant fp generation code.Nate Begeman2005-04-101-17/+2
* Fix 64 bit argument loading that straddles the args in regs / args on stackNate Begeman2005-04-101-7/+15
* Make sure that BRCOND branches can be converted into long branches too.Nate Begeman2005-04-101-1/+3
* Don't hand ISD::CALL nodes off to SelectExprFP. This fixes siod.Nate Begeman2005-04-101-1/+2
* fix ISD::BRCONDTWOWAY codegen to not deference the end() iteratorNate Begeman2005-04-091-1/+1
* do not set the root to null if an argument is deadChris Lattner2005-04-091-1/+2
* Add rlwnm instruction for variable rotateNate Begeman2005-04-091-28/+76
* Optimize FSEL a bit for fneg arguments. This fixes the recently added testNate Begeman2005-04-091-11/+12
* This target does not yet support ISD::BRCONDTWOWAYChris Lattner2005-04-091-0/+1
* 64b: Expand S/UREMNate Begeman2005-04-091-7/+27
* Optimized code sequences for setcc reg, 0Nate Begeman2005-04-071-4/+77
* PowerPC zero extends setcc resultsChris Lattner2005-04-071-0/+1
* Pattern match bitfield insert, which helps shift long by immediate, amongNate Begeman2005-04-061-15/+152
* Fixed version of optimized integer divide is now fixed. Calculate theNate Begeman2005-04-061-13/+9
* Turn off the div -> mul optimization until it works correctly 100% of theNate Begeman2005-04-061-5/+5
* Add support for MULHS and MULHU nodesNate Begeman2005-04-061-20/+192
* Back out the previous change to SelectBranchCC, since there are cases itNate Begeman2005-04-051-4/+11
* Rename canUseAsImmediateForOpcode to getImmediateForOpcode to betterNate Begeman2005-04-051-17/+23
* Implement SDIV by power of 2 as srawi/addze rather than load imm, divwNate Begeman2005-04-051-0/+24
* Pattern match fp mul-add, mul-sub, neg-mul-add, and neg-mul-subNate Begeman2005-04-041-4/+56
* Make sure that arg regs used by the call instruction are marked as such, soNate Begeman2005-04-041-15/+25
* i1 loads should also be from the low byte of the argument word.Nate Begeman2005-04-041-1/+1
* Fix i64 return, fix CopyFromRegNate Begeman2005-04-041-3/+14
* Full varargs support. All of UnitTests now passesNate Begeman2005-04-031-5/+15
* Pass the correct value for the chain to the storeNate Begeman2005-04-031-3/+2
* Fix SHL_PARTSNate Begeman2005-04-031-2/+10
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