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path: root/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
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* Rename PPC32*.h to PPC*.hChris Lattner2005-10-141-1890/+0
| | | | | | This completes the grand PPC file renaming llvm-svn: 23745
* Rename PowerPC*.h to PPC*.hChris Lattner2005-10-141-1/+1
| | | | llvm-svn: 23743
* Rename PowerPCInstrBuilder.h -> PPC*Chris Lattner2005-10-141-1/+1
| | | | llvm-svn: 23742
* Nuke PowerPCInstrFormats.h, its contents are dead. Remove the definitionsChris Lattner2005-10-141-1/+1
| | | | | | from the .td file that correspond to it llvm-svn: 23736
* another solution to the fsel issue. Instead of having 4 variants, just forceChris Lattner2005-10-021-6/+9
| | | | | | | the comparison to be 64-bits. This is fine because extensions from float to double are free. llvm-svn: 23589
* fsel can take a different FP type for the comparison and for the result. As ↵Chris Lattner2005-10-021-2/+5
| | | | | | | | such split the FSEL family into 4 things instead of just two. llvm-svn: 23588
* Modify the ppc backend to use two register classes for FP: F8RC and F4RC.Chris Lattner2005-10-011-22/+46
| | | | | | | These are used to represent float and double values, and the two regclasses contain the same physical registers. llvm-svn: 23577
* consistency with other cases, no functionality changeChris Lattner2005-09-291-0/+2
| | | | llvm-svn: 23524
* Add FP versions of the binary operators, keeping the int and fp worlds seperate.Chris Lattner2005-09-281-71/+77
| | | | llvm-svn: 23506
* PowerPC cannot truncstore i1 nativelyChris Lattner2005-09-101-1/+0
| | | | llvm-svn: 23304
* Implement i64<->fp using the fctidz/fcfid instructions on PowerPC when weNate Begeman2005-09-061-2/+10
| | | | | | | | | are allowed to generate 64-bit-only PowerPC instructions for 32 bit hosts, such as the PowerPC 970. This speeds up 189.lucas from 81.99 to 32.64 seconds. llvm-svn: 23250
* Move FCTIWZ handling out of the instruction selectors and into legalization,Chris Lattner2005-08-311-11/+4
| | | | | | getting them out of the business of making stack slots. llvm-svn: 23180
* Remove dead codeChris Lattner2005-08-311-37/+0
| | | | llvm-svn: 23179
* Remove code that is now dead from the pattern isel.Chris Lattner2005-08-311-28/+2
| | | | llvm-svn: 23177
* Handle AssertSext/AssertZext nodes, fixing the regressions last night.Chris Lattner2005-08-311-0/+4
| | | | llvm-svn: 23170
* Make fsel emission work with both the pattern and dag-dag selectors, byChris Lattner2005-08-261-1/+1
| | | | | | | | giving it a non-instruction opcode. The dag->dag selector used to not select the operands of the fsel, because it thought that whole tree was already selected. llvm-svn: 23091
* Remove some code made dead by the fsel patchNate Begeman2005-08-261-1/+0
| | | | llvm-svn: 23085
* now that fsel is formed during legalization, this code is deadChris Lattner2005-08-261-90/+0
| | | | llvm-svn: 23084
* Change ConstantPoolSDNode to actually hold the Constant itself instead ofChris Lattner2005-08-261-2/+4
| | | | | | | | putting it into the constant pool. This allows the isel machinery to create constants that it will end up deciding are not needed, without them ending up in the resultant function constant pool. llvm-svn: 23081
* Fix some warnings in an optimized buildChris Lattner2005-08-261-1/+1
| | | | llvm-svn: 23080
* add initial support for converting select_cc -> fsel in the legalizerChris Lattner2005-08-261-0/+6
| | | | | | | | | instead of in the backend. This currently handles fsel cases with registers, but doesn't have the 0.0 and -0.0 optimization enabled yet. Once this is finished, special hack for fp immediates can go away. llvm-svn: 23075
* simplify the add/sub_parts codeChris Lattner2005-08-251-16/+24
| | | | llvm-svn: 23065
* Simplify some code. It's not clear why the UDIV expanded sequenceChris Lattner2005-08-251-13/+7
| | | | | | doesn't work for large uint constants, but we'll keep the current behavior llvm-svn: 23061
* fit in 80 colsChris Lattner2005-08-251-1/+1
| | | | llvm-svn: 23051
* Split IMPLICIT_DEF into IMPLICIT_DEF_GPR and IMPLICIT_DEF_FP, so that theChris Lattner2005-08-241-3/+9
| | | | | | | instructions take a consistent reg class. Implement ISD::UNDEF in the dag->dag selector to generate this, fixing UnitTests/2003-07-06-IntOverflow. llvm-svn: 23028
* Remove some dead cases.Chris Lattner2005-08-241-7/+1
| | | | | | | | | | | | | Emit the indcall sequence as: mtctr inreg mr R12, inreg btctr If inreg and R12 aren't coallesced, this reduces the odds of having the mtctr and btctr in the same dispatch group. :) llvm-svn: 23023
* Whoops, fix a thinko. All cases except SETNE are now handled by theNate Begeman2005-08-241-11/+3
| | | | | | target independent code in SelectionDAG.cpp llvm-svn: 23002
* Add the "ppc specific" setcc-equivalent select_cc casesNate Begeman2005-08-241-4/+25
| | | | | | Prefer 'neg X' to 'subfic 0, X' since it does not set XER[CA] llvm-svn: 23000
* Make sure expressions only have one use before emitting them into a place ↵Chris Lattner2005-08-221-3/+4
| | | | | | that is conditionally executed llvm-svn: 22960
* Simplify the logic for BRTWOWAY_CC handling. The isel code alreadyChris Lattner2005-08-211-16/+7
| | | | | | | | simplifies BRTWOWAY into BR if one of the results is a fall-through. Unless I'm missing something, there is no reason to duplicate this in the target-specific code. llvm-svn: 22952
* If the false value for a select_cc is really simple (has no inputs), evaluateChris Lattner2005-08-211-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | it in the block. This codegens: int %test(bool %c) { %retval = select bool %c, int 17, int 1 ret int %retval } as: _test: rlwinm r2, r3, 0, 31, 31 li r2, 17 cmpwi cr0, r3, 0 bne .LBB_test_2 ; .LBB_test_1: ; li r2, 1 .LBB_test_2: ; or r3, r2, r2 blr instead of: _test: rlwinm r2, r3, 0, 31, 31 li r2, 17 li r4, 1 cmpwi cr0, r3, 0 bne .LBB_test_2 ; .LBB_test_1: ; or r2, r4, r4 .LBB_test_2: ; or r3, r2, r2 blr ... which is one fewer instruction. The savings are more significant for global address and constantfp nodes. llvm-svn: 22946
* Fix a bug where we were passing the wrong number of arguments to anNate Begeman2005-08-191-1/+4
| | | | | | instruction. llvm-svn: 22901
* MFLR doesn't take an operand, the LR register is implicitChris Lattner2005-08-181-1/+1
| | | | llvm-svn: 22882
* More optimal solution for loading constants.Jim Laskey2005-08-181-9/+11
| | | | llvm-svn: 22870
* Fix int foo() { return 65535; } by using the top 16 bits of the constantNate Begeman2005-08-181-20/+3
| | | | | | | | as the argument to LIS rather than the result of HA16(constant). The DAG->DAG ISel was already doing the right thing. llvm-svn: 22865
* Improve ISD::Constant codegen.Nate Begeman2005-08-181-1/+1
| | | | | | | | | | | | | | | Now for int foo() { return -1; } we generate: _foo: li r3, -1 blr instead of _foo: lis r2, -1 ori r3, r2, 65535 blr llvm-svn: 22864
* replace switch stmt with an assert, generate li 0 instead of lis 0 for 0,Chris Lattner2005-08-181-18/+15
| | | | | | to make the code follow people's expectations better. llvm-svn: 22861
* Handle loading of 0x????0000 constants with a single instruction.Jim Laskey2005-08-181-5/+9
| | | | llvm-svn: 22858
* Better version of isIntImmediate.Jim Laskey2005-08-181-1/+1
| | | | llvm-svn: 22848
* Fix a few small typos I noticed when converting this over to the DAG->DAGChris Lattner2005-08-171-12/+11
| | | | | | | selector. Also, there is no difference between addSImm and addImm, so just use addImm, folding some branches. llvm-svn: 22819
* Removed UINT_TO_FP and SINT_TO_FP from ISel outright.Jim Laskey2005-08-171-5/+0
| | | | llvm-svn: 22818
* Remove ISel code generation for UINT_TO_FP and SINT_TO_FP. Now asserts ifJim Laskey2005-08-171-34/+2
| | | | | | marked as legal. llvm-svn: 22816
* Implement a couple improvements:Nate Begeman2005-08-171-12/+28
| | | | | | | | | | | | | | | | | | | | Remove dead code in ISD::Constant handling Add support for add long, imm16 We now codegen 'long long foo(long long a) { return ++a; }' as: addic r4, r4, 1 addze r3, r3 blr instead of: li r2, 1 li r5, 0 addc r2, r4, r2 adde r3, r3, r5 blr llvm-svn: 22811
* updates for changes in nodesChris Lattner2005-08-161-10/+12
| | | | llvm-svn: 22808
* Implement BR_CC and BRTWOWAY_CC. This allows the removal of a rather nastyNate Begeman2005-08-161-18/+7
| | | | | | | fixme from the PowerPC backend. Emit slightly better code for legalizing select_cc. llvm-svn: 22805
* Pull the LLVM -> DAG lowering code out of the pattern selector so that itChris Lattner2005-08-161-484/+1
| | | | | | can be shared with the DAG->DAG selector. llvm-svn: 22799
* Broke 80 column rule.Jim Laskey2005-08-151-2/+3
| | | | llvm-svn: 22792
* Changed code gen for int to f32 to use rounding. This makes FP resultsJim Laskey2005-08-151-2/+2
| | | | | | consistent with gcc. llvm-svn: 22791
* Fix last night's PPC32 regressions byNate Begeman2005-08-141-3/+1
| | | | | | | | | 1. Not selecting the false value of a select_cc in the false arm, which isn't legal for nested selects. 2. Actually returning the node we created and Legalized in the FP_TO_UINT Expander. llvm-svn: 22789
* Make FP_TO_UINT Illegal. This allows us to generate significantly betterNate Begeman2005-08-141-71/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | codegen for FP_TO_UINT by using the legalizer's SELECT variant. Implement a codegen improvement for SELECT_CC, selecting the false node in the MBB that feeds the phi node. This allows us to codegen: void foo(int *a, int b, int c) { int d = (a < b) ? 5 : 9; *a = d; } as: _foo: li r2, 5 cmpw cr0, r4, r3 bgt .LBB_foo_2 ; entry .LBB_foo_1: ; entry li r2, 9 .LBB_foo_2: ; entry stw r2, 0(r3) blr insted of: _foo: li r2, 5 li r5, 9 cmpw cr0, r4, r3 bgt .LBB_foo_2 ; entry .LBB_foo_1: ; entry or r2, r5, r5 .LBB_foo_2: ; entry stw r2, 0(r3) blr llvm-svn: 22784
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