summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/PowerPC/PPC.h
Commit message (Collapse)AuthorAgeFilesLines
...
* Relocation enablement for PPC DAG postprocessing passBill Schmidt2013-02-211-8/+14
| | | | llvm-svn: 175693
* Initial implementation of PPCTargetTransformInfoHal Finkel2013-01-251-0/+4
| | | | | | | | | | This provides a place to add customized operation cost information and control some other target-specific IR-level transformations. The only non-trivial logic in this checkin assigns a higher cost to unaligned loads and stores (covered by the included test case). llvm-svn: 173520
* This is just a clean-up patch that simplifies the initial-exec TLS logic byBill Schmidt2012-12-131-3/+1
| | | | | | | avoiding use of machine operand flags. No change in observable behavior, so no new test cases. llvm-svn: 170141
* This patch introduces initial-exec model support for thread-local storageBill Schmidt2012-12-041-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on 64-bit PowerPC ELF. The patch includes code to handle external assembly and MC output with the integrated assembler. It intentionally does not support the "old" JIT. For the initial-exec TLS model, the ABI requires the following to calculate the address of external thread-local variable x: Code sequence Relocation Symbol ld 9,x@got@tprel(2) R_PPC64_GOT_TPREL16_DS x add 9,9,x@tls R_PPC64_TLS x The register 9 is arbitrary here. The linker will replace x@got@tprel with the offset relative to the thread pointer to the generated GOT entry for symbol x. It will replace x@tls with the thread-pointer register (13). The two test cases verify correct assembly output and relocation output as just described. PowerPC-specific selection node variants are added for the two instructions above: LD_GOT_TPREL and ADD_TLS. These are inserted when an initial-exec global variable is encountered by PPCTargetLowering::LowerGlobalTLSAddress(), and later lowered to machine instructions LDgotTPREL and ADD8TLS. LDgotTPREL is a pseudo that uses the same LDrs support added for medium code model's LDtocL, with a different relocation type. The rest of the processing is straightforward. llvm-svn: 169281
* Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form ↵Hal Finkel2012-06-081-0/+1
| | | | | | | | | | CTR-based loop branching code. This pass is derived from the Hexagon HardwareLoops pass. The only significant enhancement over the Hexagon pass is that PPCCTRLoops will also attempt to delete the replaced add and compare operations if they are no longer otherwise used. Also, invalid preheader DebugLoc is not used. llvm-svn: 158204
* Implement local-exec TLS on PowerPC.Roman Divacky2012-06-041-6/+12
| | | | llvm-svn: 157935
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-4/+1
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* Code clean up.Evan Cheng2011-07-251-5/+0
| | | | llvm-svn: 135954
* Refactor PPC target to separate MC routines from Target routines.Evan Cheng2011-07-251-5/+1
| | | | llvm-svn: 135942
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-14/+1
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-1/+4
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-1/+2
| | | | llvm-svn: 134024
* Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-271-1/+2
| | | | | | into XXXGenRegisterInfo.inc. llvm-svn: 133922
* Fix emission of PPC64 assembler on non-darwin platforms by splittingRoman Divacky2011-06-091-1/+1
| | | | | | | | VK_PPC_{HA,LO}16 into darwin and gas variants. Darwin wants {ha,lo}16(symbol) while gnu as wants symbol@{ha,l}. llvm-svn: 132802
* Wire up primitive support in the assembler backend for writing .o filesChris Lattner2010-11-151-0/+4
| | | | | | | | | | | | | | directly on the mac. This is very early, doesn't support relocations and has a terrible hack to avoid .machine from being printed, but despite that it generates an bitwise-identical-to-cctools .o file for stuff like this: define i32 @test() nounwind { ret i32 42 } I don't plan to continue pushing this forward, but if anyone else was interested in doing it, it should be really straight-forward. llvm-svn: 119136
* Implement a basic MCCodeEmitter for PPC. This doesn't handleChris Lattner2010-11-151-1/+6
| | | | | | | | | | | | | | | | fixups yet, and doesn't handle actually encoding operand values, but this is enough for llc -show-mc-encoding to show the base instruction encoding information, e.g.: mflr r0 ; encoding: [0x7c,0x08,0x02,0xa6] stw r0, 8(r1) ; encoding: [0x90,0x00,0x00,0x00] stwu r1, -64(r1) ; encoding: [0x94,0x00,0x00,0x00] Ltmp0: lhz r4, 4(r3) ; encoding: [0xa0,0x00,0x00,0x00] cmplwi cr0, r4, 8 ; encoding: [0x28,0x00,0x00,0x00] beq cr0, LBB0_2 ; encoding: [0x40,0x00,0x00,0x00] llvm-svn: 119116
* convert the operand bits into bitfields since they are all combinable inChris Lattner2010-11-151-25/+25
| | | | | | | | | different ways. Add $non_lazy_ptr support, and proper lowering for global values. Now all the ppc regression tests pass with the new instruction printer. llvm-svn: 119106
* add targetoperand flags for jump tables, constant pool and block addressChris Lattner2010-11-151-1/+16
| | | | | | | | | | | | | | nodes to indicate when ha16/lo16 modifiers should be used. This lets us pass PowerPC/indirectbr.ll. The one annoying thing about this patch is that the MCSymbolExpr isn't expressive enough to represent ha16(label1-label2) which we need on PowerPC. I have a terrible hack in the meantime, but this will have to be revisited at some point. Last major conversion item left is global variable references. llvm-svn: 119105
* implement support for the MO_DARWIN_STUB TargetOperand flag,Chris Lattner2010-11-141-0/+16
| | | | | | | | and have isel apply to to call operands as required. This allows us to get $stub suffixes on label references on ppc/tiger with the new instprinter, fixing two tests. Only 2 to go. llvm-svn: 119093
* switch PPC to a simplified MCInstLowering model.Chris Lattner2010-11-141-0/+6
| | | | llvm-svn: 119074
* fix PPC.h to not pull in TargetMachine.hChris Lattner2010-11-141-2/+2
| | | | llvm-svn: 119072
* tidy some targets.Chris Lattner2010-02-021-2/+0
| | | | llvm-svn: 95146
* remove dead code.Chris Lattner2010-02-021-4/+0
| | | | llvm-svn: 95141
* Add new helpers for registering targets.Daniel Dunbar2009-07-251-3/+0
| | | | | | - Less boilerplate == good. llvm-svn: 77052
* Put Target definitions inside Target specific header, and llvm namespace.Daniel Dunbar2009-07-181-0/+4
| | | | llvm-svn: 76344
* Reapply TargetRegistry refactoring commits.Daniel Dunbar2009-07-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | --- Reverse-merging r75799 into '.': U test/Analysis/PointerTracking U include/llvm/Target/TargetMachineRegistry.h U include/llvm/Target/TargetMachine.h U include/llvm/Target/TargetRegistry.h U include/llvm/Target/TargetSelect.h U tools/lto/LTOCodeGenerator.cpp U tools/lto/LTOModule.cpp U tools/llc/llc.cpp U lib/Target/PowerPC/PPCTargetMachine.h U lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp U lib/Target/PowerPC/PPCTargetMachine.cpp U lib/Target/PowerPC/PPC.h U lib/Target/ARM/ARMTargetMachine.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/ARMTargetMachine.h U lib/Target/ARM/ARM.h U lib/Target/XCore/XCoreTargetMachine.cpp U lib/Target/XCore/XCoreTargetMachine.h U lib/Target/PIC16/PIC16TargetMachine.cpp U lib/Target/PIC16/PIC16TargetMachine.h U lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp U lib/Target/Alpha/AlphaTargetMachine.cpp U lib/Target/Alpha/AlphaTargetMachine.h U lib/Target/X86/X86TargetMachine.h U lib/Target/X86/X86.h U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h U lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h U lib/Target/X86/X86TargetMachine.cpp U lib/Target/MSP430/MSP430TargetMachine.cpp U lib/Target/MSP430/MSP430TargetMachine.h U lib/Target/CppBackend/CPPTargetMachine.h U lib/Target/CppBackend/CPPBackend.cpp U lib/Target/CBackend/CTargetMachine.h U lib/Target/CBackend/CBackend.cpp U lib/Target/TargetMachine.cpp U lib/Target/IA64/IA64TargetMachine.cpp U lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp U lib/Target/IA64/IA64TargetMachine.h U lib/Target/IA64/IA64.h U lib/Target/MSIL/MSILWriter.cpp U lib/Target/CellSPU/SPUTargetMachine.h U lib/Target/CellSPU/SPU.h U lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp U lib/Target/CellSPU/SPUTargetMachine.cpp U lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp U lib/Target/Mips/MipsTargetMachine.cpp U lib/Target/Mips/MipsTargetMachine.h U lib/Target/Mips/Mips.h U lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp U lib/Target/Sparc/SparcTargetMachine.cpp U lib/Target/Sparc/SparcTargetMachine.h U lib/ExecutionEngine/JIT/TargetSelect.cpp U lib/Support/TargetRegistry.cpp llvm-svn: 75820
* Revert 75762, 75763, 75766..75769, 75772..75775, 75778, 75780, 75782 to ↵Stuart Hastings2009-07-151-1/+1
| | | | | | | | repair broken LLVM-GCC build. Will revert 75770 in the llvm-gcc trunk. llvm-svn: 75799
* Register Target's TargetMachine and AsmPrinter in the new registry.Daniel Dunbar2009-07-151-1/+1
| | | | | | | - This abuses TargetMachineRegistry's constructor for now, this will get cleaned up in time. llvm-svn: 75762
* Have asm printers use formatted_raw_ostream directly to avoid aDavid Greene2009-07-141-2/+3
| | | | | | dynamic_cast<>. llvm-svn: 75670
* Add the Object Code Emitter class. Original patch by Aaron Gray, I did someBruno Cardoso Lopes2009-07-061-1/+4
| | | | | | cleanup, removed some #includes and moved Object Code Emitter out-of-line. llvm-svn: 74813
* Remove unused AsmPrinter OptLevel argument, and propogate.Daniel Dunbar2009-07-011-3/+2
| | | | | | | - This more or less amounts to a revert of r65379. I'm curious to know what happened that caused this variable to become unused. llvm-svn: 74579
* First patch in the direction of splitting MachineCodeEmitter in two subclasses:Bruno Cardoso Lopes2009-05-301-0/+2
| | | | | | JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray llvm-svn: 72631
* Instead of passing in an unsigned value for the optimization level, use an enum,Bill Wendling2009-04-291-1/+3
| | | | | | | which better identifies what the optimization is doing. And is more flexible for future uses. llvm-svn: 70440
* Second attempt:Bill Wendling2009-04-291-1/+1
| | | | | | | | | | | | Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'll change the JIT with a follow-up patch. llvm-svn: 70343
* r70270 isn't ready yet. Back this out. Sorry for the noise.Bill Wendling2009-04-281-1/+1
| | | | llvm-svn: 70275
* Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want toBill Wendling2009-04-281-1/+1
| | | | | | | | | | | use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'm not 100% sure if it's necessary to change it there... llvm-svn: 70270
* CodeGen still defaults to non-verbose asm, but llc now overrides it and ↵Evan Cheng2009-03-251-1/+1
| | | | | | default to verbose. llvm-svn: 67668
* Overhaul my earlier submission due to feedback. It's a large patch, but most ofBill Wendling2009-02-241-1/+2
| | | | | | | | | | | | them are generic changes. - Use the "fast" flag that's already being passed into the asm printers instead of shoving it into the DwarfWriter. - Instead of calling "MI->getParent()->getParent()" for every MI, set the machine function when calling "runOnMachineFunction" in the asm printers. llvm-svn: 65379
* Tidy up #includes, deleting a bunch of unnecessary #includes.Dan Gohman2009-01-051-3/+0
| | | | llvm-svn: 61715
* Use raw_ostream throughout the AsmPrinter.Owen Anderson2008-08-211-1/+2
| | | | llvm-svn: 55092
* Use PassManagerBase instead of FunctionPassManager for functionsDan Gohman2008-03-111-1/+0
| | | | | | | | that merely add passes. This allows them to be used with either FunctionPassManager or PassManager, or even with a custom new kind of pass manager. llvm-svn: 48256
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Moved the MachOWriter and ELFWriter out of the Target/* files. Placed theBill Wendling2007-02-081-2/+0
| | | | | | | | definition of it into the CodeGen library. This is so that a backend doesn't necessarily add in these writers if it doesn't use them (like in the lli program). llvm-svn: 34034
* start using PPC predicates more consistently.Chris Lattner2006-11-171-15/+0
| | | | llvm-svn: 31833
* encode BLR predicate info for the JITChris Lattner2006-11-041-10/+10
| | | | llvm-svn: 31450
* Go through all kinds of trouble to mark 'blr' as having a predicate operandChris Lattner2006-11-041-8/+23
| | | | | | | | | | that takes a register and condition code. Print these pieces of BLR the right way, even though it is currently set to 'always'. Next up: get the JIT encoding right, then enhance branch folding to produce predicated blr for simple examples. llvm-svn: 31449
* The DarwinAsmPrinter need not check for isDarwin. createPPCAsmPrinterPassChris Lattner2006-09-201-2/+2
| | | | | | should create the right asmprinter subclass. llvm-svn: 30542
* Separate target specific asm properties from the asm printers.Jim Laskey2006-09-061-1/+2
| | | | llvm-svn: 30126
* Completely rearchitect the interface between targets and the pass manager.Chris Lattner2006-09-041-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | This pass: 1. Splits TargetMachine into TargetMachine (generic targets, can be implemented any way, like the CBE) and LLVMTargetMachine (subclass of TM that is used by things using libcodegen and other support). 2. Instead of having each target fully populate the passmgr for file or JIT output, move all this to common code, and give targets hooks they can implement. 3. Commonalize the target population stuff between file emission and JIT emission. 4. All (native code) codegen stuff now happens in a FunctionPassManager, which paves the way for "fast -O0" stuff in the CFE later, and now LLC could lazily stream .bc files from disk to use less memory. 5. There are now many fewer #includes and the targets don't depend on the scalar xforms or libanalysis anymore (but codegen does). 6. Changing common code generator pass ordering stuff no longer requires touching all targets. 7. The JIT now has the option of "-fast" codegen or normal optimized codegen, which is now orthogonal to the fact that JIT'ing is being done. llvm-svn: 30081
* Initial checkin of the Mach-O emitter. There's plenty of fixmes, but itNate Begeman2006-08-231-1/+8
| | | | | | does emit linkable .o files in very simple cases. llvm-svn: 29850
OpenPOWER on IntegriCloud