| Commit message (Collapse) | Author | Age | Files | Lines |
| ... | |
| |
|
|
|
|
|
| |
We do use a very small set of physical registers, so account for
them in the virtual register encoding between MachineInstr and MC
llvm-svn: 187799
|
| |
|
|
|
|
|
|
|
| |
This change converts the NVPTX target to use the MC infrastructure
instead of directly emitting MachineInstr instances. This brings
the target more up-to-date with LLVM TOT, and should fix PR15175
and PR15958 (libNVPTXInstPrinter is empty) as a side-effect.
llvm-svn: 187798
|
| |
|
|
|
|
|
|
|
| |
each corresponding CodeGen.
Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel.
It races to emit *.inc files simultaneously.
llvm-svn: 187780
|
| |
|
|
| |
llvm-svn: 186844
|
| |
|
|
|
|
| |
.ftz to instructions if the nvptx-f32ftz attribute is set to "true"
llvm-svn: 186820
|
| |
|
|
|
|
|
| |
Intrinsics already existed for the 64-bit variants, so these support operations
of size at most 32-bits.
llvm-svn: 186392
|
| |
|
|
|
|
| |
size.
llvm-svn: 186274
|
| |
|
|
|
|
| |
specifying the vector size.
llvm-svn: 185606
|
| |
|
|
|
|
|
| |
Since we were explicitly not calling AsmPrinter::doInitialization,
any module-scope inline asm was not being printed.
llvm-svn: 185336
|
| |
|
|
| |
llvm-svn: 185335
|
| |
|
|
|
|
|
|
| |
We are using virtual registers throughout now, but we still need
to keep a few physical registers per class around to keep the
infrastructure happy.
llvm-svn: 185334
|
| |
|
|
| |
llvm-svn: 185333
|
| |
|
|
|
|
| |
some typos
llvm-svn: 185332
|
| |
|
|
|
|
|
|
| |
Fix a case where we were incorrectly sign-extending a value when we should have been zero-extending the value.
Also change some SIGN_EXTEND to ANY_EXTEND because we really dont care and may have more opportunity to fold subexpressions
llvm-svn: 185331
|
| |
|
|
| |
llvm-svn: 185330
|
| |
|
|
| |
llvm-svn: 185329
|
| |
|
|
|
|
| |
value
llvm-svn: 185328
|
| |
|
|
|
|
| |
Avoids unused variable warnings in release builds.
llvm-svn: 185271
|
| |
|
|
|
|
| |
This makes it more consistent with the ZeroOrNegativeOneBooleanContent flag
llvm-svn: 185179
|
| |
|
|
| |
llvm-svn: 185178
|
| |
|
|
|
|
|
|
| |
Fix ABI handling for function
returning bool -- use st.param.b32 to return the value
and use ld.param.b32 in caller to load the return value.
llvm-svn: 185177
|
| |
|
|
| |
llvm-svn: 185176
|
| |
|
|
|
|
|
|
| |
instructions from their patterns
Test case is no breakage
llvm-svn: 185175
|
| |
|
|
|
|
| |
rather poor and we're better off just ignoring it and letting LLVM expand all i8 ops out to i16.
llvm-svn: 185174
|
| |
|
|
| |
llvm-svn: 185173
|
| |
|
|
|
|
| |
vector parameter loads
llvm-svn: 185172
|
| |
|
|
| |
llvm-svn: 185171
|
| |
|
|
|
|
|
|
|
|
|
| |
No functionality change.
It should suffice to check the type of a debug info metadata, instead of
calling Verify. For cases where we know the type of a DI metadata, use
assert.
Also update testing cases to make them conform to the format of DI classes.
llvm-svn: 185135
|
| |
|
|
|
|
| |
This reverts commit r185020
llvm-svn: 185032
|
| |
|
|
|
|
|
|
| |
No functionality change.
It should suffice to check the type of a debug info metadata, instead of
calling Verify.
llvm-svn: 185020
|
| |
|
|
| |
llvm-svn: 184831
|
| |
|
|
|
|
|
|
| |
of NVPTXTargetObjectFile. ~NVPTXTargetObjectFile() tries to delete them.
It caused crash on some hosts since r184595.
llvm-svn: 184728
|
| |
|
|
| |
llvm-svn: 184642
|
| |
|
|
|
|
| |
IR for CUDA should use "nvptx[64]-nvidia-cuda", and IR for NV OpenCL should use "nvptx[64]-nvidia-nvcl"
llvm-svn: 184579
|
| |
|
|
|
|
| |
use it.
llvm-svn: 184369
|
| |
|
|
|
|
| |
anymore and causes constants to be emitted in the global address space
llvm-svn: 183652
|
| |
|
|
|
|
| |
Fixes a leak found by valgrind.
llvm-svn: 183031
|
| |
|
|
|
|
|
|
|
|
|
|
| |
Now that 3.3 is branched, we are re-enabling virtual registers to help
iron out bugs before the next release. Some of the post-RA passes do
not play well with virtual registers, so we disable them for now. The
needed functionality of the PrologEpilogInserter pass is copied to a
new backend-specific NVPTXPrologEpilog pass.
The test for this commit is not breaking the existing tests.
llvm-svn: 182998
|
| |
|
|
|
|
| |
ld.u1 instead of an ld.u8.
llvm-svn: 182924
|
| |
|
|
|
|
|
|
|
|
|
|
| |
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.
Patch by Xiaoyi Guo!
This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.
llvm-svn: 182885
|
| |
|
|
|
|
| |
Not only does this break encapsulation, it's gross.
llvm-svn: 182876
|
| |
|
|
|
|
|
| |
Remove the old IR ordering mechanism and switch to new one. Fix unit
test failures.
llvm-svn: 182704
|
| |
|
|
|
|
|
| |
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
llvm-svn: 182703
|
| |
|
|
|
|
| |
while there.
llvm-svn: 182594
|
| |
|
|
| |
llvm-svn: 182590
|
| |
|
|
| |
llvm-svn: 182394
|
| |
|
|
|
|
| |
symbol name error in the output PTX.
llvm-svn: 182298
|
| |
|
|
| |
llvm-svn: 182297
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This converter currently only handles global variables in address space 0. For
these variables, they are promoted to address space 1 (global memory), and all
uses are updated to point to the result of a cvta.global instruction on the new
variable.
The motivation for this is address space 0 global variables are illegal since we
cannot declare variables in the generic address space. Instead, we place the
variables in address space 1 and explicitly convert the pointer to address
space 0. This is primarily intended to help new users who expect to be able to
place global variables in the default address space.
llvm-svn: 182254
|
| |
|
|
|
|
| |
need to use .u8 for i1 parameters for kernels.
llvm-svn: 182253
|