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* [mips] Fix atomic operations at O0, v3Aleksandar Beserminji2018-07-058-337/+1058
| | | | | | | | | | | | | | | | | | | | | | | Similar to PR/25526, fast-regalloc introduces spills at the end of basic blocks. When this occurs in between an ll and sc, the stores can cause the atomic sequence to fail. This patch fixes the issue by introducing more pseudos to represent atomic operations and moving their lowering to after the expansion of postRA pseudos. This version addresses issues with the initial implementation and covers all atomic operations. This resolves PR/32020. Thanks to James Cowgill for reporting the issue! Patch By: Simon Dardis Differential Revision: https://reviews.llvm.org/D31287 llvm-svn: 336328
* [mips] Warn when crc, ginv, virt flags are used with too old revisionVladimir Stefanovic2018-07-042-11/+33
| | | | | | | | | CRC and GINV ASE require revision 6, Virtualization requires revision 5. Print a warning when revision is older than required. Differential Revision: https://reviews.llvm.org/D48843 llvm-svn: 336296
* [MIPS GlobalISel] Lower arguments using stackPetar Jovanovic2018-07-032-10/+96
| | | | | | | | | | | Lower more than 4 arguments using stack. This patch targets MIPS32. It supports only functions with arguments of type i32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D47934 llvm-svn: 336185
* [Mips][FastISel] Do not duplicate condition while lowering branchesPetar Jovanovic2018-07-021-4/+1
| | | | | | | | | | | | | | | | This change fixes the issue that arises when we duplicate condition from the predecessor block. If the condition's arguments are not considered alive across the blocks, fast regalloc gets confused and starts generating reloads from the slots that have never been spilled to. This change also leads to smaller code given that, unlike on architectures with condition codes, on Mips we can branch directly on register value, thus we gain nothing by duplication. Patch by Dragan Mladjenovic. Differential Revision: https://reviews.llvm.org/D48642 llvm-svn: 336084
* [mips] Support shrink-wrappingPetar Jovanovic2018-06-293-11/+11
| | | | | | | | | | Except for -O0, it's enabled by default. Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D47947 llvm-svn: 335989
* Add Triple::isMIPS()/isMIPS32()/isMIPS64(). NFCAlexander Richardson2018-06-254-13/+6
| | | | | | | | | | | | | | There are quite a few if statements that enumerate all these cases. It gets even worse in our fork of LLVM where we also have a Triple::cheri (which is mips64 + CHERI instructions) and we had to update all if statements that check for Triple::mips64 to also handle Triple::cheri. This patch helps to reduce our diff to upstream and should also make some checks more readable. Reviewed By: atanasyan Differential Revision: https://reviews.llvm.org/D48548 llvm-svn: 335493
* [mips][ias] Enable IAS by default for OpenBSD / FreeBSD mips64/mips64el.Brad Smith2018-06-241-0/+5
| | | | | | | | Reviewers: atanasyan Differential Review: https://reviews.llvm.org/D31557 llvm-svn: 335434
* [mips] Modify comment to test new email address (NFC).Simon Dardis2018-06-211-1/+1
| | | | llvm-svn: 335269
* [mips] Add microMIPS specific addressing patterns.Simon Dardis2018-06-202-91/+113
| | | | | | | | | | | | | These are identical but use microMIPS instructions instead of MIPS instructions. Also, flatten the 'let AdditionalPredicates = [InMicroMips]' by using the ISA_MICROMIPS adjective. Add tests for constant materialization. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D48275 llvm-svn: 335185
* [mips] Correct predicates for loads, bit manipulation instructions and some ↵Simon Dardis2018-06-204-22/+33
| | | | | | | | | | | | pseudos Additionally, correct the definition of the rdhwr instruction. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D48216 llvm-svn: 335162
* [mips] Fix the predicates of some DSP instructions from AdditionalPredicates ↵Simon Dardis2018-06-203-8/+8
| | | | | | | | | | to ASEPredicate Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D48166 llvm-svn: 335122
* [mips] Mark microMIPS64 as being unsupported.Simon Dardis2018-06-192-0/+5
| | | | | | | | | | There are no provided instruction definitions for this architecture. Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D48320 llvm-svn: 335057
* [mips] Fix the predicates of some aliasesSimon Dardis2018-06-192-3/+6
| | | | | | | | | | | Previously, some aliases were marked as not being available for microMIPS32R6, but this was overridden at the top level. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D48321 llvm-svn: 335053
* [mips] Add licensing information of the microMIPS tablegen files. (NFC)Simon Dardis2018-06-152-0/+26
| | | | llvm-svn: 334827
* [mips] Correct predicates for MSA pseudo instructionsSimon Dardis2018-06-141-1/+2
| | | | llvm-svn: 334708
* [mips][microMIPS] Extending size reduction pass with LWP and SWPZoran Jovanovic2018-06-134-55/+245
| | | | | | | | | | | | Author: milena.vujosevic.janicic Reviewers: sdardis The patch extends size reduction pass for MicroMIPS. It introduces reduction of two instructions into one instruction: Two SW instructions are transformed into one SWP instrucition. Two LW instructions are transformed into one LWP instrucition. Differential Revision: https://reviews.llvm.org/D39115 llvm-svn: 334595
* [mips] Guard some floating point instructions correctlySimon Dardis2018-06-121-31/+37
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47636 llvm-svn: 334491
* [mips] Extend LONG_BRANCH_LUi/ADDiu with extra parameterAleksandar Beserminji2018-06-123-22/+67
| | | | | | | | | | | Extend LONG_BRANCH_LUi and LONG_BRANCH_ADDiu pseudo instructions with additional flag, so instead of always lowering to lui %hi(...), addiu %lo(...) or addiu %hi(...), now they can lower to either %lo, %hi, %higher or %highest depending on the added flag. Differential Revision: https://reviews.llvm.org/D47941 llvm-svn: 334490
* [mips] Fix spill slot for mips3, n64 abiAleksandar Beserminji2018-06-111-3/+4
| | | | | | | | | | | | | | When program is compiled for mips3 with n64 abi, wrong register class is used for creating an emergency spill slot. This patch fixes the correct register class to be chosen. This patch resolves PR35859. Thanks to John Baldwin for reporting the issue! Differential Revision: https://reviews.llvm.org/D47938 llvm-svn: 334419
* [mips] Correct the predicates for a number of codegen only instructionsSimon Dardis2018-06-081-37/+52
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47638 llvm-svn: 334280
* [Mips] Silencing warnings in instruction info (NFC)Petar Jovanovic2018-06-071-12/+18
| | | | | | | | | | | isORCopyInst and isReadOrWriteToDSPReg functions were producing warning that some statements my fall through. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D47876 llvm-svn: 334194
* Change TII isCopyInstr way of returning arguments(NFC)Petar Jovanovic2018-06-064-17/+19
| | | | | | | | | | | Make TII isCopyInstr() return MachineOperands through pointer to pointer instead via reference. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D47364 llvm-svn: 334105
* [MC] Pass MCSubtargetInfo to fixupNeedsRelaxation and applyFixupPeter Smith2018-06-062-3/+6
| | | | | | | | | | | | | | | | | | On targets like Arm some relaxations may only be performed when certain architectural features are available. As functions can be compiled with differing levels of architectural support we must make a judgement on whether we can relax based on the MCSubtargetInfo for the function. This change passes through the MCSubtargetInfo for the function to fixupNeedsRelaxation so that the decision on whether to relax can be made per function. In this patch, only the ARM backend makes use of this information. We must also pass the MCSubtargetInfo to applyFixup because some fixups skip error checking on the assumption that relaxation has occurred, to prevent code-generation errors applyFixup must see the same MCSubtargetInfo as fixupNeedsRelaxation. Differential Revision: https://reviews.llvm.org/D44928 llvm-svn: 334078
* [MIPS GlobalISel] Add lowerCallPetar Jovanovic2018-06-062-1/+133
| | | | | | | | | | | | Add minimal support to lower function calls. Support only functions with arguments/return that go through registers and have type i32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D45627 llvm-svn: 334071
* [Mips] Remove uneeded variants of ADDC/ADDE loweringAmaury Sechet2018-06-054-48/+5
| | | | | | | | | | | | Summary: As it turns out, the lowering for the Mips16* family of target is the exact same thing as what the ops expands to, so the code handling them can be removed and the ops only enabled for the MipsSE* family of targets. Reviewers: smaksimovic, atanasyan, abeserminji Subscribers: sdardis, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D47703 llvm-svn: 334052
* [mips] Fix the predicates for arithmetic operationsSimon Dardis2018-06-052-51/+55
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47635 llvm-svn: 334031
* [mips] Restore the availablity of trap for microMIPSSimon Dardis2018-06-041-0/+1
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47584 llvm-svn: 333895
* [mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructionsSimon Atanasyan2018-06-011-53/+30
| | | | | | | | | | | | | | | The `MipsAsmParser::loadImmediate` can load immediates of various sizes into a register. Idea of this change is to use `loadImmediate` in the `MipsAsmParser::expandMemInst` method to load offset into a register and then call required load/store instruction. The patch removes separate `expandLoadInst` and `expandStoreInst` methods and does everything in the `expandMemInst` method to escape code duplication. Differential Revision: https://reviews.llvm.org/D47316 llvm-svn: 333774
* [mips] Extend list of relocations supported by the `.reloc` directiveSimon Atanasyan2018-06-013-1/+80
| | | | | | | Supporting GOT and TLS related relocations by the `.reloc` directive is useful for purpose of testing various tools like a linker, for example. llvm-svn: 333773
* Set ADDE/ADDC/SUBE/SUBC to expand by defaultAmaury Sechet2018-06-011-10/+3
| | | | | | | | | | | | | | | Summary: They've been deprecated in favor of UADDO/ADDCARRY or USUBO/SUBCARRY for a while. Target that uses these opcodes are changed in order to ensure their behavior doesn't change. Reviewers: efriedma, craig.topper, dblaikie, bkramer Subscribers: jholewinski, arsenm, jyknight, sdardis, nemanjai, nhaehnle, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, mgrang, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D47422 llvm-svn: 333748
* [mips] Guard more aliases correctly.Simon Dardis2018-06-012-48/+56
| | | | | | Also, duplicate an alias for microMIPS. llvm-svn: 333741
* [mips] Guard 'nop' properly and add mips16's nop instructionSimon Dardis2018-06-013-12/+19
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47583 llvm-svn: 333739
* [mips] Select the correct instruction for computing frameindexesSimon Dardis2018-06-014-3/+7
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47582 llvm-svn: 333736
* [GlobalISel][Mips] LegalizerInfo verifier: Adding LegalizerInfo::verify(...) ↵Roman Tereshin2018-05-311-0/+2
| | | | | | | | | | | | call for Mips Reviewers: aemerson, qcolombet Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D46339 llvm-svn: 333665
* [mips] Guard all short instructions correctly.Simon Dardis2018-05-312-22/+40
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47533 llvm-svn: 333645
* [mips] Correct the definition of CTC2/CFC2Simon Dardis2018-05-301-8/+6
| | | | llvm-svn: 333542
* [mips] Correct the predicates of microMIPS compact branch instructionsSimon Dardis2018-05-301-6/+4
| | | | llvm-svn: 333541
* [mips] Sink PredicateControl further down the class hierarchy.Simon Dardis2018-05-3011-68/+59
| | | | | | | | | | | | | | | | Previously PredicateControl in some cases was a member of <X>Inst classes for some X (DSP, EVA) or was in more irregular place in the hierarchry for any given instruction. This patch moves PredicateControl down to the root so that it is consistently available. Then correct the base class of microMIPS instructions as using EncodingPredicates instead of the general Predicates field of Instruction. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D47526 llvm-svn: 333536
* [mips] Correct the predicates of arithmetic and logic instructions.Simon Dardis2018-05-303-45/+79
| | | | | | | | | | | | As part of this effort, duplicate and correct the predicates of some aliases. Also disable code generation of some short form instructions for FastISel, as it would otherwise reject them. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D47075 llvm-svn: 333530
* DAG: Remove redundant version of getRegisterTypeForCallingConvMatt Arsenault2018-05-292-10/+0
| | | | | | | | | | | There seems to be no real reason to have these separate copies. The existing implementations just copy each other for x86. For Mips there is a subtle difference, which is just a bug since it changes based on the context where which one was called. Dropping this version, all tests pass. If I try to merge them to match the removed version, a test fails. llvm-svn: 333440
* [mips] Process numeric register name in the .set assignment directiveSimon Atanasyan2018-05-291-8/+44
| | | | | | | | | | | | | | | | | | | | | | | | Now LLVM assembler cannot process the following code and generates an error. GNU tools support .set assignment directive with numeric register name. ``` .set r4, 4 test.s:1:11: error: invalid token in expression .set r4, $4 ^ ``` This patch teach assembler to handle such directives correctly. Unfortunately a numeric register name cannot be represented as an expression. That's why we have to maintain a separate `StringMap` in the `MipsAsmParser` to keep mapping between aliases names and register numbers. Differential revision: https://reviews.llvm.org/D47464 llvm-svn: 333428
* [mips] Emit R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO16 / HI16 ↵Simon Atanasyan2018-05-294-12/+36
| | | | | | | | | | | | | relocations Emit R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO16 and R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_HI16 chains of relocations for %lo(%neg(%gp_rel())) and %hi(%neg(%gp_rel())) expressions in case of microMIPS. Differential Revision: http://reviews.llvm.org/D47220 llvm-svn: 333409
* [mips] Emit R_MICROMIPS_HIGHER / R_MICROMIPS_HIGHEST relocationsSimon Atanasyan2018-05-294-4/+18
| | | | | | | | | | | Emit R_MICROMIPS_HIGHER / R_MICROMIPS_HIGHEST relocations for %higher() and %highest() expressions in case of microMIPS. These relocations do exactly the same things as R_MIPS_HIGHER / R_MIPS_HIGHEST, but for consistency it's better to write microMIPS variants. Differential Revision: http://reviews.llvm.org/D47219 llvm-svn: 333407
* [mips] Correct the predicates for a number of instructions.Simon Dardis2018-05-291-21/+25
| | | | | | | | | | Previously, their listed predicates were overridden at the scope level. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46947 llvm-svn: 333405
* [mips] Cleanup the code to reduce diff with the upcoming patches. NFCSimon Atanasyan2018-05-291-10/+10
| | | | llvm-svn: 333404
* [mips] Escape else-after-return. NFCSimon Atanasyan2018-05-291-62/+63
| | | | llvm-svn: 333403
* [mips] Stop parsing a .set assignment if the first argument is not an identifierSimon Atanasyan2018-05-291-3/+2
| | | | | | | | | | | | | | Before this fix the following code triggers two error messages. The second one is at least useless: test.s:1:9: error: expected identifier after .set .set 123, $a0 ^ test-set.s:1:9: error: unexpected token, expected comma .set 123, $a0 ^ llvm-svn: 333402
* [mips] Fix the definitions of lwp, swpSimon Dardis2018-05-255-68/+26
| | | | | | | | | | | | | Rather than using a regpair operand of these instructions, use two seperate operands and a custom converter to handle the implicit second register operand. Additionally, remove the microMIPS32R6 definition as its redundant. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D47255 llvm-svn: 333288
* [mips] Remove duplicated code from the expandLoadInst. NFCSimon Atanasyan2018-05-241-36/+17
| | | | llvm-svn: 333164
* [mips] Remove redundant argument from expandLoadInst/expandStoreInst. NFCSimon Atanasyan2018-05-241-15/+13
| | | | llvm-svn: 333163
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