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* [mips] '.set at=$0' should be equivalent to '.set noat'Daniel Sanders2014-03-251-1/+1
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D3171 llvm-svn: 204714
* [mips] Correct testcase for .set at=$reg and emit the new warnings for ↵Daniel Sanders2014-03-251-11/+19
| | | | | | | | | | | | | | | | | | numeric registers too. Summary: Remove the XFAIL added in my previous commit and correct the test such that it correctly tests the expansion of the assembler temporary. Also added a test to check that $at is always $1 when written by the user. Corrected the new assembler temporary warnings so that they are emitted for numeric registers too. Differential Revision: http://llvm-reviews.chandlerc.com/D3169 llvm-svn: 204711
* [mips] Fix assembler temporary expansion and add associated warnings about ↵Daniel Sanders2014-03-251-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | the use of $at. Summary: The assembler temporary is normally $at ($1) but can be reassigned using '.set at=$reg'. Regardless of which register is nominated as the assembler temporary, $at remains $1 when written by the user. Adds warnings under the following conditions: * The register nominated as the assembler temporary is used by the user. * '.set noat' is in effect and $at is used by the user. Both of these only work for named registers. I have a follow up commit that makes it work for numeric registers as well. XFAIL set-at-directive.s since it incorrectly tests that $at is redefined by '.set at=$reg'. Testcases will follow in a separate commit. Patch by David Chisnall His work was sponsored by: DARPA, AFRL Differential Revision: http://llvm-reviews.chandlerc.com/D3167 llvm-svn: 204710
* [mips] Add error message when trying to use $at in '.set noat' mode.Daniel Sanders2014-03-241-1/+6
| | | | | | | | | | Summary: Patch by David Chisnall His work was sponsored by: DARPA, AFRL Differential Revision: http://llvm-reviews.chandlerc.com/D3158 llvm-svn: 204621
* [mips] Allow dsubu to take an immediate as an alias for dsubiu.Daniel Sanders2014-03-241-0/+3
| | | | | | | | | | Summary: Patch by David Chisnall His work was sponsored by: DARPA, AFRL Differential Revision: http://llvm-reviews.chandlerc.com/D3155 llvm-svn: 204611
* [mips] Implement shorthand add / sub forms for MIPS.Daniel Sanders2014-03-243-1/+94
| | | | | | | | | | | | | | | | | | | | | Summary: - If only two registers are passed to a three-register operation, then the first argument is both source and destination register. - If a non-register is passed as the last argument, generate the immediate version of the instruction. Also mark DADD commutative and add scheduling information (to the generic scheduler), and implement DSUB. Patch by David Chisnall His work was sponsored by: DARPA, AFRL CC: theraven Differential Revision: http://llvm-reviews.chandlerc.com/D3148 llvm-svn: 204605
* remove a bunch of unused private methodsNuno Lopes2014-03-232-23/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | found with a smarter version of -Wunused-member-function that I'm playwing with. Appologies in advance if I removed someone's WIP code. include/llvm/CodeGen/MachineSSAUpdater.h | 1 include/llvm/IR/DebugInfo.h | 3 lib/CodeGen/MachineSSAUpdater.cpp | 10 -- lib/CodeGen/PostRASchedulerList.cpp | 1 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 10 -- lib/IR/DebugInfo.cpp | 12 -- lib/MC/MCAsmStreamer.cpp | 2 lib/Support/YAMLParser.cpp | 39 --------- lib/TableGen/TGParser.cpp | 16 --- lib/TableGen/TGParser.h | 1 lib/Target/AArch64/AArch64TargetTransformInfo.cpp | 9 -- lib/Target/ARM/ARMCodeEmitter.cpp | 12 -- lib/Target/ARM/ARMFastISel.cpp | 84 -------------------- lib/Target/Mips/MipsCodeEmitter.cpp | 11 -- lib/Target/Mips/MipsConstantIslandPass.cpp | 12 -- lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 21 ----- lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 2 lib/Target/PowerPC/PPCFastISel.cpp | 1 lib/Transforms/Instrumentation/AddressSanitizer.cpp | 2 lib/Transforms/Instrumentation/BoundsChecking.cpp | 2 lib/Transforms/Instrumentation/MemorySanitizer.cpp | 1 lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 8 - lib/Transforms/Scalar/SCCP.cpp | 1 utils/TableGen/CodeEmitterGen.cpp | 2 24 files changed, 2 insertions(+), 261 deletions(-) llvm-svn: 204560
* [mips] Correct lowering of VECTOR_SHUFFLE to VSHF.Daniel Sanders2014-03-211-1/+8
| | | | | | | | | | | | | | | | | | | | | Summary: VECTOR_SHUFFLE concatenates the vectors in an vectorwise fashion. <0b00, 0b01> + <0b10, 0b11> -> <0b00, 0b01, 0b10, 0b11> VSHF concatenates the vectors in a bitwise fashion: <0b00, 0b01> + <0b10, 0b11> -> 0b0100 + 0b1110 -> 0b01001110 <0b10, 0b11, 0b00, 0b01> We must therefore swap the operands to get the correct result. The test case that discovered the issue was MultiSource/Benchmarks/nbench. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3142 llvm-svn: 204480
* [mips] Update namespace.Matheus Almeida2014-03-211-5/+1
| | | | | | | We should be using the llvm namespace and not an anonymous namespace in a header file. llvm-svn: 204450
* [MIPS] Add cpu octeon and some instructionsKai Nacke2014-03-2010-6/+118
| | | | | | | | | | The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
* Provide an operand for microMIPS wait instruction.Zoran Jovanovic2014-03-203-5/+18
| | | | llvm-svn: 204329
* Implementation of microMIPS 16-bit instructions MOVE and JALR.Zoran Jovanovic2014-03-207-10/+117
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D3112 llvm-svn: 204325
* Mark alias symbols as microMIPS if necessary. Differential Revision: ↵Zoran Jovanovic2014-03-202-0/+21
| | | | | | http://llvm-reviews.chandlerc.com/D3080 llvm-svn: 204323
* [mips] Splitting up class definition from implementation.Matheus Almeida2014-03-202-129/+171
| | | | | | | | Also removed some unnecessary #includes. No functional changes. llvm-svn: 204320
* [mips] 80-column.Matheus Almeida2014-03-191-8/+12
| | | | llvm-svn: 204252
* Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changingOwen Anderson2014-03-131-1/+1
| | | | | | | | | | operator* on the by-operand iterators to return a MachineOperand& rather than a MachineInstr&. At this point they almost behave like normal iterators! Again, this requires making some existing loops more verbose, but should pave the way for the big range-based for-loop cleanups in the future. llvm-svn: 203865
* Try harder to evaluate expressions when printing assembly.Rafael Espindola2014-03-121-3/+1
| | | | | | | | | When printing assembly we don't have a Layout object, but we can still try to fold some constants. Testcase by Ulrich Weigand. llvm-svn: 203677
* [mips][fp64] Add an implicit def to MTHC1 claiming that it reads the lower ↵Daniel Sanders2014-03-121-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | 32-bits of 64-bit FPR Summary: This is a white lie to workaround a widespread bug in the -mfp64 implementation. The problem is that none of the 32-bit fpu ops mention the fact that they clobber the upper 32-bits of the 64-bit FPR. This allows MTHC1 to be scheduled on the wrong side of most 32-bit FPU ops, particularly MTC1. Fixing that requires a major overhaul of the FPU implementation which can't be done right now due to time constraints. The testcase is SingleSource/Benchmarks/Misc/oourafft.c when given TARGET_CFLAGS='-mips32r2 mfp64 -mmsa'. Also correct the comment added in r203464 to indicate that two instructions were affected. Reviewers: matheusalmeida, jacksprat Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3029 llvm-svn: 203659
* [mips] BSEL's and BINS[RL] operands are reversed compared to the vselect ↵Daniel Sanders2014-03-123-17/+42
| | | | | | | | | | | | | | | | | | | | | | | node used in the pattern. Summary: Correct the match patterns and the lowerings that made the CodeGen tests pass despite the mistakes. The original testcase that discovered the problem was SingleSource/UnitTests/SignlessType/factor.c in test-suite. During review, we also found that some of the existing CodeGen tests were incorrect and fixed them: * bitwise.ll: In bsel_v16i8 the IfSet/IfClear were reversed because bsel and bmnz have different operand orders and the test didn't correctly account for this. bmnz goes 'IfClear, IfSet, CondMask', while bsel goes 'CondMask, IfClear, IfSet'. * vec.ll: In the cases where a bsel is emitted as a bmnz (they are the same operation with a different input tied to the result) the operands were in the wrong order. * compare.ll and compare_float.ll: The bsel operand order was correct for a greater-than comparison, but a greater-than comparison instruction doesn't exist. Lowering this operation inverts the condition so the IfSet/IfClear need to be swapped to match. The differences between BSEL, BMNZ, and BMZ and how they map to/from vselect are rather confusing. I've therefore added a note to MSA.txt to explain this in a single place in addition to the comments that explain each case. Reviewers: matheusalmeida, jacksprat Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3028 llvm-svn: 203657
* Replace '#include ValueTypes.h' with forward declarations.Patrik Hagglund2014-03-123-3/+0
| | | | | | | In some cases the include is pushed "downstream" (or removed if unused). llvm-svn: 203644
* [mips] Implement NaCl sandboxing of function calls:Sasa Stankovic2014-03-111-2/+56
| | | | | | | | | * Add masking instructions before indirect calls (in MC layer). * Align call + branch delay to the bundle end (in MC layer). Differential Revision: http://llvm-reviews.chandlerc.com/D3032 llvm-svn: 203606
* [mips] Implement NaCl sandboxing of loads, stores and SP changes:Sasa Stankovic2014-03-103-5/+123
| | | | | | | | | | * Add masking instructions before loads and stores (in MC layer). * Add masking instructions after SP changes (in MC layer). * Forbid loads, stores and SP changes in delay slots (in MI layer). Differential Revision: http://llvm-reviews.chandlerc.com/D2904 llvm-svn: 203484
* Fix regression with -O0 for mips .Reed Kotler2014-03-101-0/+12
| | | | llvm-svn: 203469
* [mips][fp64] Add an implicit def to MFHC1 claiming that it reads the lower ↵Daniel Sanders2014-03-101-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 32-bits of 64-bit FPR Summary: This is a white lie to workaround a widespread bug in the -mfp64 implementation. The problem is that none of the 32-bit fpu ops mention the fact that they clobber the upper 32-bits of the 64-bit FPR. This allows MFHC1 to be scheduled on the wrong side of most 32-bit FPU ops. Fixing that requires a major overhaul of the FPU implementation which can't be done right now due to time constraints. MFHC1 is one of two affected instructions. These instructions are the only FPU instructions that don't read or write the lower 32-bits. We therefore pretend that it reads the bottom 32-bits to artificially create a dependency and prevent the scheduler changing the behaviour of the code. The other instruction is MTHC1 which will be fixed once I've have found a failing test case for it. The testcase is test-suite/SingleSource/UnitTests/Vector/simple.c when given TARGET_CFLAGS="-mips32r2 -mfp64 -mmsa". Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2966 llvm-svn: 203464
* [mips] Assembly parser must invoke the target streamer to handle .set ↵Matheus Almeida2014-03-101-0/+1
| | | | | | reorder macro. llvm-svn: 203459
* Replace PROLOG_LABEL with a new CFI_INSTRUCTION.Rafael Espindola2014-03-073-36/+34
| | | | | | | | | | | | | | | | | | | | | | | The old system was fairly convoluted: * A temporary label was created. * A single PROLOG_LABEL was created with it. * A few MCCFIInstructions were created with the same label. The semantics were that the cfi instructions were mapped to the PROLOG_LABEL via the temporary label. The output position was that of the PROLOG_LABEL. The temporary label itself was used only for doing the mapping. The new CFI_INSTRUCTION has a 1:1 mapping to MCCFIInstructions and points to one by holding an index into the CFI instructions of this function. I did consider removing MMI.getFrameInstructions completelly and having CFI_INSTRUCTION own a MCCFIInstruction, but MCCFIInstructions have non trivial constructors and destructors and are somewhat big, so the this setup is probably better. The net result is that we don't create temporary labels that are never used. llvm-svn: 203204
* [Layering] Move DebugInfo.h into the IR library where its implementationChandler Carruth2014-03-063-3/+3
| | | | | | already lives. llvm-svn: 203046
* This patch implements .set dsp directive and sets appropriate feature ↵Vladimir Medic2014-03-053-0/+17
| | | | | | bits.This directive is a counterpart of -mattr=dsp command line option with the exception that it does not influence elf header flags. The usage example is gives in test file. llvm-svn: 202966
* [mips][msa] Correct the behaviour of the COPY_FW pseudo on lanes 2 and 3.Daniel Sanders2014-03-041-1/+1
| | | | | | | | | | Summary: Previously, attempting to extract lanes 2 and 3 would actually extract lane 1. The MSA CodeGen tests only covered lanes 0 and 1. Differential Revision: http://llvm-reviews.chandlerc.com/D2935 llvm-svn: 202848
* [Modules] Move CFG.h to the IR library as it defines graph traits overChandler Carruth2014-03-043-3/+3
| | | | | | IR types. llvm-svn: 202827
* [Modules] Move ValueMap to the IR library. While this class does notChandler Carruth2014-03-041-1/+1
| | | | | | | | | | | | directly care about the Value class (it is templated so that the key can be any arbitrary Value subclass), it is in fact concretely tied to the Value class through the ValueHandle's CallbackVH interface which relies on the key type being some Value subclass to establish the value handle chain. Ironically, the unittest is already in the right library. llvm-svn: 202824
* [Modules] Move InstIterator out of the Support library, where it had noChandler Carruth2014-03-041-1/+1
| | | | | | | | | | | | | business. This header includes Function and BasicBlock and directly uses the interfaces of both classes. It has to do with the IR, it even has that in the name. =] Put it in the library it belongs to. This is one step toward making LLVM's Support library survive a C++ modules bootstrap. llvm-svn: 202814
* [cleanup] Re-sort all the includes with utils/sort_includes.py.Chandler Carruth2014-03-046-7/+7
| | | | llvm-svn: 202811
* This patch implements .set mips32r2 directive and sets appropriate feature ↵Vladimir Medic2014-03-043-0/+35
| | | | | | bits. It also introduces helper functions that are used to set and clear feature bits as necessary. This directive is a counterpart of -mips32r2 command line options with the exception that it does not influence elf header flags. The usage example is gives in test file. llvm-svn: 202807
* Cleaning up a bunch of pre-Visual C++ 2012 build hacks.Yaron Keren2014-03-041-8/+0
| | | | llvm-svn: 202806
* [mips] Prevent %lo relocation being used on MSA loads and stores.Daniel Sanders2014-03-036-75/+102
| | | | | | | | | | | | | | | | | Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 llvm-svn: 202717
* [mips] support FK_Data_2 and FK_Data_8 to fix big-endian debug dataEd Maste2014-03-031-0/+4
| | | | | | | | | This fixes invalid lengths in .debug_aranges on big-endian mips64 (lengths appear to be left-shifted by 32 bits) and in .debug_loc. Differential Revision: http://llvm-reviews.chandlerc.com/D2517 llvm-svn: 202716
* Fixing a build failure reported by certain buildbots. This will disable ↵Vladimir Medic2014-03-031-1/+1
| | | | | | jalx instruction for micromips target. llvm-svn: 202715
* This patch implements jalx instruction for Mips architecture.This ↵Vladimir Medic2014-03-031-0/+1
| | | | | | instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well. llvm-svn: 202706
* [C++11] Replace llvm::tie with std::tie.Benjamin Kramer2014-03-021-1/+2
| | | | | | The old implementation is no longer needed in C++11. llvm-svn: 202644
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-027-37/+33
| | | | | | Remove the old functions. llvm-svn: 202636
* Switch all uses of LLVM_OVERRIDE to just use 'override' directly.Craig Topper2014-03-024-10/+8
| | | | llvm-svn: 202621
* Now that we have C++11, turn simple functors into lambdas and remove a ton ↵Benjamin Kramer2014-03-011-16/+6
| | | | | | | | of boilerplate. No intended functionality change. llvm-svn: 202588
* Fixed operand of SC microMIPS instruction.Zoran Jovanovic2014-02-282-1/+5
| | | | llvm-svn: 202526
* Fixed encoding of SYSCALL microMIPS instruction.Zoran Jovanovic2014-02-281-1/+1
| | | | llvm-svn: 202523
* Revert revision 202518 because of wrong commit message.Zoran Jovanovic2014-02-281-1/+1
| | | | llvm-svn: 202521
* Fix operand of SC instruction.Zoran Jovanovic2014-02-281-1/+1
| | | | llvm-svn: 202518
* Reorder Mips/MCTargetDesc/CMakeLists.txt.NAKAMURA Takumi2014-02-281-1/+1
| | | | llvm-svn: 202483
* [mips] Add MipsNaClELFStreamer.cpp to CMakeLists.txt.Sasa Stankovic2014-02-281-0/+1
| | | | llvm-svn: 202482
* [mips] Implement NaCl sandboxing of indirect jumps:Sasa Stankovic2014-02-285-3/+170
| | | | | | | | | * Align targets of indirect jumps to instruction bundle boundaries (in MI layer). * Add masking instructions before indirect jumps (in MC layer). Differential Revision: http://llvm-reviews.chandlerc.com/D2847 llvm-svn: 202479
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