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* Make pseudos FEXT_CCRX16_ins and FEXT_CCRXI16_ins into custom emitters.Reed Kotler2013-02-255-69/+70
| | | | llvm-svn: 176007
* Make psuedo FEXT_T8I816_ins into a custom emitter.Reed Kotler2013-02-245-61/+39
| | | | llvm-svn: 176002
* Make psuedo FEXT_T8I816_ins a custom inserter. It should be expandedReed Kotler2013-02-244-22/+34
| | | | | | as early as possible; which means during instruction selection. llvm-svn: 175984
* Add new base instruction def for cmpi, cmp, slt and sltu so that def/usesReed Kotler2013-02-231-5/+10
| | | | | | proper. Fixed this already a few days ago for slti. llvm-svn: 175975
* Expand pseudos/macros for Selt. This is the last of the complexReed Kotler2013-02-233-0/+82
| | | | | | macros.The rest is some small misc. stuff. llvm-svn: 175950
* [mips] Emit call16 operator instead of got_disp. The former allows lazy binding.Akira Hatanaka2013-02-221-3/+1
| | | | llvm-svn: 175920
* Fix a nomenclature mistake. Slt->Slti in the functions. The "i" refersReed Kotler2013-02-222-8/+8
| | | | | | to the immediate operand of sli or cmp function. llvm-svn: 175865
* Expand mips16 SelT form pseudso/macros.Reed Kotler2013-02-223-0/+81
| | | | llvm-svn: 175862
* Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky2013-02-218-51/+47
| | | | | | | | | | | | | | | to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. llvm-svn: 175788
* Expand the sel pseudo/macro. This generates basic blocks where previouslyReed Kotler2013-02-213-1/+97
| | | | | | | there were inline br .+4 instructions. Soon everything can enjoy the full instruction scheduling experience. llvm-svn: 175718
* Mips specific standalone assembler addressing mode %hi and %lo.Jack Carter2013-02-211-0/+5
| | | | | | | | | | | | The constructs %hi() and %lo() represent the high and low 16 bits of the address. Because the 16 bit offset field of an LW instruction is interpreted as signed, if bit 15 of the low part is 1 then the low part will act as a negative and 1 needs to be added to the high part. Contributer: Vladimir Medic llvm-svn: 175707
* ELF symbol table field st_other support, Jack Carter2013-02-201-85/+84
| | | | | | | | | | | | | | | | | | | | excluding visibility bits. Mips specific standalone assembler directive "set at". This directive changes the general purpose register that the assembler will use when given the symbolic register name $at. This does not include negative testing. That will come in a future patch. A side affect of this patch recognizes the different GPR register names for temporaries between old abi and new abi so a test case for that is included. Contributer: Vladimir Medic llvm-svn: 175686
* MCParser: Update method names per coding guidelines.Jim Grosbach2013-02-201-19/+19
| | | | | | | | | | | | | | | | | | | s/AddDirectiveHandler/addDirectiveHandler/ s/ParseMSInlineAsm/parseMSInlineAsm/ s/ParseIdentifier/parseIdentifier/ s/ParseStringToEndOfStatement/parseStringToEndOfStatement/ s/ParseEscapedString/parseEscapedString/ s/EatToEndOfStatement/eatToEndOfStatement/ s/ParseExpression/parseExpression/ s/ParseParenExpression/parseParenExpression/ s/ParseAbsoluteExpression/parseAbsoluteExpression/ s/CheckForValidSection/checkForValidSection/ http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly No functional change intended. llvm-svn: 175675
* Update TargetLowering ivars for name policy.Jim Grosbach2013-02-201-1/+1
| | | | | | | | | | | http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly ivars should be camel-case and start with an upper-case letter. A few in TargetLowering were starting with a lower-case letter. No functional change intended. llvm-svn: 175667
* Fix the (clang -Werror) build by removing an unused member variable.David Blaikie2013-02-201-2/+1
| | | | llvm-svn: 175607
* Expand pseudos/macros:Reed Kotler2013-02-203-10/+110
| | | | | | | | SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16 $T8 shows up as register $24 when emitted from C++ code so we had to change some tests that were already there for this functionality. llvm-svn: 175593
* ELF symbol table field st_other support, Jack Carter2013-02-191-0/+4
| | | | | | | | | | | | excluding visibility bits. Mips (o32 abi) specific e_header setting. EF_MIPS_ABI_O32 needs to be set in the ELF header flags for o32 abi output. Contributer: Reed Kotler llvm-svn: 175569
* ELF symbol table field st_other support, Jack Carter2013-02-191-1/+4
| | | | | | | | | | | | excluding visibility bits. Mips (Mips16) specific e_header setting. EF_MIPS_ARCH_ASE_M16 needs to be set in the ELF header flags for Mips16. Contributer: Reed Kotler llvm-svn: 175566
* ELF symbol table field st_other support, Jack Carter2013-02-194-6/+36
| | | | | | | | | | | excluding visibility bits. Mips (MicroMips) specific STO handling . The st_other field settig for STO_MIPS_MICROMIPS Contributer: Zoran Jovanovic llvm-svn: 175564
* Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16,Reed Kotler2013-02-192-1/+48
| | | | | | BtnezT8SltiX16, BtnezT8SltiuX16 . llvm-svn: 175486
* Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.Reed Kotler2013-02-193-0/+58
| | | | llvm-svn: 175474
* Expand macro/pseudo instructions BtnezT8SltX16 and BtnezT8SltuX16.Reed Kotler2013-02-181-0/+8
| | | | llvm-svn: 175420
* Expand pseudo/macro BteqzT8SltuX16 . There is no test case becauseReed Kotler2013-02-182-0/+7
| | | | | | | | at this time, llvm is generating a different but equivalent pattern that would lead to this instruction. I am trying to think of a way to get it to generate this. If I can't, I may just remove the pseudo. llvm-svn: 175419
* Expand pseudo/macro BteqzT8SltX16.Reed Kotler2013-02-181-0/+3
| | | | llvm-svn: 175417
* Expand macro/pseudo BteqzT8CmpX16.Reed Kotler2013-02-181-0/+3
| | | | llvm-svn: 175416
* Beginning of expanding all current mips16 macro/pseudo instruction sequences.Reed Kotler2013-02-183-3/+34
| | | | | | | | | | This expansion will be moved to expandISelPseudos as soon as I can figure out how to do that. There are other instructions which use this ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all, I will delete the macro asm string text so it has no way to be used in the future. llvm-svn: 175413
* Clean up mips16 td file in preparation for massive pseudo lowering work.Reed Kotler2013-02-161-71/+68
| | | | llvm-svn: 175379
* One more try to make this look nice. I have lots of pseudo lowering Reed Kotler2013-02-162-4/+12
| | | | | | | | as well as 16/32 bit variants to do and so I want this to look nice when I do it. I've been experimenting with this. No new test cases are needed. llvm-svn: 175369
* Use a different scheme to chose 16/32 variants. This scheme is moreReed Kotler2013-02-162-11/+7
| | | | | | | consistent with how BuildMI works. No new tests needed. All should work the same as before. llvm-svn: 175342
* [mips] Remove SDNPWantParent from the list of SDNodeProperties.Akira Hatanaka2013-02-162-17/+14
| | | | | | No functionality change intended. llvm-svn: 175325
* [mips] Clean up class MipsCCInfo.Akira Hatanaka2013-02-152-58/+74
| | | | | | No functionality change intended. llvm-svn: 175310
* [mips] Split SelectAddr, which was used to match address patterns, into twoAkira Hatanaka2013-02-153-18/+71
| | | | | | | | | | | functions. Set AddedComplexity to determine the order in which patterns are matched. This simplifies selection of floating point loads/stores. No functionality change intended. llvm-svn: 175300
* Remove a final dependency on the form field in tablegen; which is a remnantReed Kotler2013-02-152-6/+10
| | | | | | | of the old jit and which we don't intend to support in mips16 or micromips. This dependency is for the testing of whether an instruction is a pseudo. llvm-svn: 175297
* Fix minor mips16 issues in directives for function prologue. Probably this doesReed Kotler2013-02-151-7/+10
| | | | | | | not matter but makes it more gcc compatible which avoids possible subtle problems. Also, turned back on a disabled check in helloworld.ll. llvm-svn: 175237
* [mips] Disallow moving load/store instructions past volatile instructions.Akira Hatanaka2013-02-141-1/+1
| | | | | | | Unfortunately, I wasn't able to create a test case that demonstrates the problem I was trying to fix with this patch. llvm-svn: 175226
* [mips] Replace usage of SmallSet with BitVector, which is used to keep track ofAkira Hatanaka2013-02-141-86/+83
| | | | | | | defined and used registers. Also add a few helper functions to simplify the code. llvm-svn: 175224
* [mips] Fix comments and coding style violations. Declare functions to be const.Akira Hatanaka2013-02-141-64/+47
| | | | llvm-svn: 175222
* [mips] Simplify code in function Filler::findDelayInstr.Akira Hatanaka2013-02-141-38/+29
| | | | | | | | 1. Define and use function terminateSearch. 2. Use MachineBasicBlock::iterator instead of MachineBasicBlock::instr_iterator. 3. Delete the line which checks whether an instruction is a pseudo. llvm-svn: 175219
* Remove the form field from Mips16 instruction formats and set thingsReed Kotler2013-02-143-87/+73
| | | | | | | | | up so that we can apply the direct object emitter patch. This patch should be a nop right now and it's test is to not break what is already there. llvm-svn: 175126
* For Mips 16, add the optimization where the 16 bit form of addiu sp can be usedReed Kotler2013-02-133-3/+46
| | | | | | | | | | if the offset fits in 11 bits. This makes use of the fact that the abi requires sp to be 8 byte aligned so the actual offset can fit in 8 bits. It will be shifted left and sign extended before being actually used. The assembler or direct object emitter will shift right the 11 bit signed field by 3 bits. We don't need to deal with that here. llvm-svn: 175073
* Make jumptables work for -staticReed Kotler2013-02-131-0/+2
| | | | llvm-svn: 175044
* [mips] Expand pseudo instructions before they are emitted inAkira Hatanaka2013-02-111-11/+38
| | | | | | | | | | | | | | | | | | | | | | | | | MipsCodeEmitter.cpp. JALR and NOP are expanded by function emitPseudoExpansionLowering, which is not called when the old JIT is used. This fixes the following tests which have been failing on llvm-mips-linux builder: LLVM :: ExecutionEngine__2003-01-04-LoopTest.ll LLVM :: ExecutionEngine__2003-05-06-LivenessClobber.ll LLVM :: ExecutionEngine__2003-06-04-bzip2-bug.ll LLVM :: ExecutionEngine__2005-12-02-TailCallBug.ll LLVM :: ExecutionEngine__2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll LLVM :: ExecutionEngine__hello2.ll LLVM :: ExecutionEngine__stubs.ll LLVM :: ExecutionEngine__test-branch.ll LLVM :: ExecutionEngine__test-call.ll LLVM :: ExecutionEngine__test-common-symbols.ll LLVM :: ExecutionEngine__test-loadstore.ll LLVM :: ExecutionEngine__test-loop.ll llvm-svn: 174912
* [mips] Fix indentation.Akira Hatanaka2013-02-111-41/+39
| | | | llvm-svn: 174907
* Add the 16 bit version of addiu. To the assembler, the 16 and 32 bit are theReed Kotler2013-02-082-0/+21
| | | | | | | | | | same so we put in the comment field an indicator when we think we are emitting the 16 bit version. For the direct object emitter, the difference is important as well as for other passes which need an accurate count of program size. There will be other similar putbacks to this for various instructions. llvm-svn: 174747
* When Mips16 frames grow large, the immediate field may exceed the maximumReed Kotler2013-02-083-10/+90
| | | | | | | | allowed size for the instruction. This code uses RegScavenger to fix this. We sometimes need 2 registers for Mips16 so we must handle things differently than how register scavenger is normally used. llvm-svn: 174696
* [mips] Make Filler a class and reduce indentation.Akira Hatanaka2013-02-071-34/+38
| | | | llvm-svn: 174666
* [mips] Add definition of JALR instruction which has two register operands. ↵Akira Hatanaka2013-02-073-3/+14
| | | | | | | | Change the original JALR instruction with one register operand to be a pseudo-instruction. llvm-svn: 174657
* Make sure we call externals from libraries properly when -static.Reed Kotler2013-02-071-0/+3
| | | | | | For example, when we are doing mips16 hard float or soft float. llvm-svn: 174583
* Enable jumps when in -static mode.Reed Kotler2013-02-071-1/+1
| | | | llvm-svn: 174580
* [mips] Make NOP a pseudo instruction and expand it to "sll $zero, $zero, 0".Akira Hatanaka2013-02-063-15/+7
| | | | llvm-svn: 174546
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