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* [mips] Do not use function CC_MipsN_VarArg unless the function being analyzedAkira Hatanaka2013-02-051-1/+1
| | | | | | | | | | | is a vararg function. The original code was examining flag OutputArg::IsFixed to determine whether CC_MipsN_VarArg or CC_MipsN should be called. This is not correct, since this flag is often set to false when the function being analyzed is a non-variadic function. llvm-svn: 174442
* Move MRI liveouts to Mips return instructions.Jakob Stoklund Olesen2013-02-052-16/+12
| | | | llvm-svn: 174410
* This patch that sets the Mips ELF header flag for Jack Carter2013-02-054-1/+12
| | | | | | | | MicroMips architectures. Contributer: Zoran Jovanovic llvm-svn: 174360
* This patch that sets the EmitAlias flag in td files Jack Carter2013-02-054-36/+56
| | | | | | | | | | | | | and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
* This patch changes a static_cast to dyn_castJack Carter2013-02-052-3/+7
| | | | | | | | for MipsELFStreamer objects. Contributer: Jack Carter llvm-svn: 174354
* Start static relocation implementation for mips16.Reed Kotler2013-02-022-1/+30
| | | | | | This checkin makes hello world work. llvm-svn: 174264
* [PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier2013-01-312-11/+5
| | | | | | | Each target implementation was needlessly recomputing the index. Part of rdar://13076458 llvm-svn: 174083
* Removing initializer for the field removed in r173887David Blaikie2013-01-301-1/+1
| | | | llvm-svn: 173888
* Remove unused variable (introduced in r173884) to clear clang -Werror buildDavid Blaikie2013-01-301-2/+0
| | | | llvm-svn: 173887
* Forgot to add new file to CMakeListsJack Carter2013-01-301-0/+1
| | | | llvm-svn: 173886
* This patch implements runtime Mips specificJack Carter2013-01-306-3/+113
| | | | | | | | setting of ELF header e_flags. Contributer: Jack Carter llvm-svn: 173884
* This patch reworks how llvm targets set Jack Carter2013-01-301-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | and update ELF header e_flags. Currently gathering information such as symbol, section and data is done by collecting it in an MCAssembler object. From MCAssembler and MCAsmLayout objects ELFObjectWriter::WriteObject() forms and streams out the ELF object file. This patch just adds a few members to the MCAssember class to store and access the e_flag settings. It allows for runtime additions to the e_flag by assembler directives. The standalone assembler can get to MCAssembler from getParser().getStreamer().getAssembler(). This patch is the generic infrastructure and will be followed by patches for ARM and Mips for their target specific use. Contributer: Jack Carter llvm-svn: 173882
* [mips] Lower EH_RETURN.Akira Hatanaka2013-01-3010-2/+184
| | | | | | Patch by Sasa Stankovic. llvm-svn: 173862
* Teach SDISel to combine fsin / fcos into a fsincos node if the followingEvan Cheng2013-01-291-0/+2
| | | | | | | | | | | | | | | | | | conditions are met: 1. They share the same operand and are in the same BB. 2. Both outputs are used. 3. The target has a native instruction that maps to ISD::FSINCOS node or the target provides a sincos library call. Implemented the generic optimization in sdisel and enabled it for Mac OSX. Also added an additional optimization for x86_64 Mac OSX by using an alternative entry point __sincos_stret which returns the two results in xmm0 / xmm1. rdar://13087969 PR13204 llvm-svn: 173755
* Remove addToNoHelperNeeded function that was left unused after r173649. ↵Craig Topper2013-01-281-6/+0
| | | | | | Fixes a -Wunused warning. llvm-svn: 173664
* Make some code a little simpler.Reed Kotler2013-01-282-40/+40
| | | | llvm-svn: 173649
* fix use of std::std. it's ordered set.Reed Kotler2013-01-261-3/+3
| | | | llvm-svn: 173563
* This patch implements parsing the .wordJack Carter2013-01-251-7/+42
| | | | | | | | directive for the Mips assembler. Contributer: Vladimir Medic llvm-svn: 173407
* [mips] Set flag neverHasSideEffects flag on some of the floating point ↵Akira Hatanaka2013-01-251-12/+8
| | | | | | instructions. llvm-svn: 173401
* MipsISelLowering.cpp: Fill unreachable paths to fix warnings. ↵NAKAMURA Takumi2013-01-241-0/+6
| | | | | | | | [-Wsometimes-uninitialized] FIXME: Could they, unreachable(s), be removed? FIXME: I could prefer the coding standards... llvm-svn: 173325
* MipsISelLowering.cpp: Fix a warning, take two. [-Wunused-variable]NAKAMURA Takumi2013-01-241-2/+2
| | | | | | ...and fix a typo, s/#ifdef/#ifndef/ llvm-svn: 173324
* MipsISelLowering.cpp: Fix a warning. [-Wunused-variable]NAKAMURA Takumi2013-01-241-3/+5
| | | | llvm-svn: 173323
* The next phase of Mips16 hard float implementation.Reed Kotler2013-01-242-36/+246
| | | | | | | | | | | | | | | | Allow Mips16 routines to call Mips32 routines that have abi requirements that either arguments or return values are passed in floating point registers. This handles only the pic case. We have not done non pic for Mips16 yet in any form. The libm functions are Mips32, so with this addition we have a complete Mips16 hard float implementation. We still are not able to complete mix Mip16 and Mips32 with hard float. That will be the next phase which will have several steps. For Mips32 to freely call Mips16 some stub functions must be created. llvm-svn: 173320
* Clean up assignment of CalleeSaveStackSlotSize: get rid of the default and ↵Eli Bendersky2013-01-231-2/+3
| | | | | | explicitly set this in every target that needs to change it from the default. llvm-svn: 173270
* [mips] Implement MipsRegisterInfo::getRegPressureLimit.Akira Hatanaka2013-01-222-0/+24
| | | | llvm-svn: 173197
* [mips] Clean up code in MipsTargetLowering::LowerCall. No functional changeAkira Hatanaka2013-01-222-21/+14
| | | | | | intended llvm-svn: 173189
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-196-34/+52
| | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Formatting fixes. Mostly long lines and blank spaces at end of lines. Contributer: Jack Carter llvm-svn: 172882
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-188-1/+145
| | | | | | | | | | | | | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Support for Mips register information sections. Mips ELF object files have a section that is dedicated to register use info. Some of this information such as the assumed Global Pointer value is used by the linker in relocation resolution. The register info file is .reginfo in o32 and .MIPS.options in 64 and n32 abi files. This patch contains the changes needed to create the sections, but leaves the actual register accounting for a future patch. Contributer: Jack Carter llvm-svn: 172847
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-182-47/+57
| | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic llvm-svn: 172842
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-173-2/+24
| | | | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic llvm-svn: 172685
* reverting 172579Jack Carter2013-01-163-21/+2
| | | | llvm-svn: 172594
* Akira,Jack Carter2013-01-163-2/+21
| | | | | | | | | | | | Hope you are feeling better. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic llvm-svn: 172579
* This patch fixes a Mips specific bug where Jack Carter2013-01-151-1/+7
| | | | | | | | | | | we need to generate a N64 compound relocation R_MIPS_GPREL_32/R_MIPS_64/R_MIPS_NONE. The bug was exposed by the SingleSourcetest case DuffsDevice.c. Contributer: Jack Carter llvm-svn: 172496
* Improve r172471: avoid all those extra casts on the lines nearbyDmitri Gribenko2013-01-141-4/+6
| | | | llvm-svn: 172481
* Fix CastingDavid Greene2013-01-141-1/+2
| | | | | | Fix a casting-away-const compiler warning. llvm-svn: 172471
* MipsDisassembler.cpp: Prune DecodeHWRegs64RegisterClass() to suppress a ↵NAKAMURA Takumi2013-01-121-16/+0
| | | | | | warning. [-Wunused-function] llvm-svn: 172319
* MipsAsmParser: Try to unbreak tests to add extra check.NAKAMURA Takumi2013-01-121-2/+2
| | | | llvm-svn: 172315
* This patch tackles the problem of parsing Mips Jack Carter2013-01-127-237/+496
| | | | | | | | | | | | | | | | | | register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
* This patch produces the correct addend value forJack Carter2013-01-081-0/+1
| | | | | | | | an R_MIPS_GPREL16 relocation. Contributer: Jack Carter llvm-svn: 171882
* This patch produces the correct pointer size Jack Carter2013-01-081-0/+4
| | | | | | | | | | | | value in the 64 bit .eh_frame section. It doesn't however allow exception handling to work yet since it depends on the correct relocation model being set in the ELF header flags. Contributer: Jack Carter llvm-svn: 171881
* Renamed MCInstFragment to MCRelaxableFragment and added some comments.Eli Bendersky2013-01-081-1/+1
| | | | | | No change in functionality. llvm-svn: 171822
* Change SMRange to be half-open (exclusive end) instead of closed (inclusive)Jordan Rose2013-01-071-27/+23
| | | | | | | | | | This is necessary not only for representing empty ranges, but for handling multibyte characters in the input. (If the end pointer in a range refers to a multibyte character, should it point to the beginning or the end of the character in a char array?) Some of the code in the asm parsers was already assuming this anyway. llvm-svn: 171765
* Remove # from the beginning and end of def names. The # is a paste operator ↵Craig Topper2013-01-072-27/+27
| | | | | | and should only be used with something to paste on either side. llvm-svn: 171697
* Switch TargetTransformInfo from an immutable analysis pass that requiresChandler Carruth2013-01-072-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a TargetMachine to construct (and thus isn't always available), to an analysis group that supports layered implementations much like AliasAnalysis does. This is a pretty massive change, with a few parts that I was unable to easily separate (sorry), so I'll walk through it. The first step of this conversion was to make TargetTransformInfo an analysis group, and to sink the nonce implementations in ScalarTargetTransformInfo and VectorTargetTranformInfo into a NoTargetTransformInfo pass. This allows other passes to add a hard requirement on TTI, and assume they will always get at least on implementation. The TargetTransformInfo analysis group leverages the delegation chaining trick that AliasAnalysis uses, where the base class for the analysis group delegates to the previous analysis *pass*, allowing all but tho NoFoo analysis passes to only implement the parts of the interfaces they support. It also introduces a new trick where each pass in the group retains a pointer to the top-most pass that has been initialized. This allows passes to implement one API in terms of another API and benefit when some other pass above them in the stack has more precise results for the second API. The second step of this conversion is to create a pass that implements the TargetTransformInfo analysis using the target-independent abstractions in the code generator. This replaces the ScalarTargetTransformImpl and VectorTargetTransformImpl classes in lib/Target with a single pass in lib/CodeGen called BasicTargetTransformInfo. This class actually provides most of the TTI functionality, basing it upon the TargetLowering abstraction and other information in the target independent code generator. The third step of the conversion adds support to all TargetMachines to register custom analysis passes. This allows building those passes with access to TargetLowering or other target-specific classes, and it also allows each target to customize the set of analysis passes desired in the pass manager. The baseline LLVMTargetMachine implements this interface to add the BasicTTI pass to the pass manager, and all of the tools that want to support target-aware TTI passes call this routine on whatever target machine they end up with to add the appropriate passes. The fourth step of the conversion created target-specific TTI analysis passes for the X86 and ARM backends. These passes contain the custom logic that was previously in their extensions of the ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces. I separated them into their own file, as now all of the interface bits are private and they just expose a function to create the pass itself. Then I extended these target machines to set up a custom set of analysis passes, first adding BasicTTI as a fallback, and then adding their customized TTI implementations. The fourth step required logic that was shared between the target independent layer and the specific targets to move to a different interface, as they no longer derive from each other. As a consequence, a helper functions were added to TargetLowering representing the common logic needed both in the target implementation and the codegen implementation of the TTI pass. While technically this is the only change that could have been committed separately, it would have been a nightmare to extract. The final step of the conversion was just to delete all the old boilerplate. This got rid of the ScalarTargetTransformInfo and VectorTargetTransformInfo classes, all of the support in all of the targets for producing instances of them, and all of the support in the tools for manually constructing a pass based around them. Now that TTI is a relatively normal analysis group, two things become straightforward. First, we can sink it into lib/Analysis which is a more natural layer for it to live. Second, clients of this interface can depend on it *always* being available which will simplify their code and behavior. These (and other) simplifications will follow in subsequent commits, this one is clearly big enough. Finally, I'm very aware that much of the comments and documentation needs to be updated. As soon as I had this working, and plausibly well commented, I wanted to get it committed and in front of the build bots. I'll be doing a few passes over documentation later if it sticks. Commits to update DragonEgg and Clang will be made presently. llvm-svn: 171681
* [mips] Fix data layout string. Add 64 to the list of native integer widthsAkira Hatanaka2013-01-051-4/+6
| | | | | | and add stack alignment information. llvm-svn: 171587
* [mips] MipsTargetLowering::getSetCCResultType should return a vector type ifAkira Hatanaka2013-01-041-1/+3
| | | | | | vectors are being compared. llvm-svn: 171517
* [mips] 80 columns.Akira Hatanaka2013-01-044-8/+14
| | | | llvm-svn: 171515
* [mips] Reorder template parameters. Remove class shift_rotate_imm32 andAkira Hatanaka2013-01-042-54/+59
| | | | | | shift_rotate_imm64. llvm-svn: 171513
* [mips] Refactor conditional move instructions.Akira Hatanaka2013-01-041-13/+20
| | | | llvm-svn: 171511
* [mips] Refactor instructions which move data from or to coprocessors.Akira Hatanaka2013-01-043-33/+34
| | | | llvm-svn: 171510
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