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* [mips] Implement the 'dext' aliases and it's disassembly alias.Simon Dardis2017-09-145-43/+162
| | | | | | | | | | | | | | | | The other members of the dext family of instructions (dextm, dextu) are traditionally handled by the assembler selecting the right variant of 'dext' depending on the values of the position and size operands. When these instructions are disassembled, rather than reporting the actual instruction, an equivalent aliased form of 'dext' is generated and is reported. This is to mimic the behaviour of binutils. Reviewers: slthakur, nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D34887 llvm-svn: 313276
* [mips] Implement the 'dins' aliases.Simon Dardis2017-09-145-25/+139
| | | | | | | | | | | | Traditionally GAS has provided automatic selection between dins, dinsm and dinsu. Binutils also disassembles all instructions in that family as 'dins' rather than the actual instruction. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D34877 llvm-svn: 313267
* Test commit.Aleksandar Beserminji2017-09-141-1/+1
| | | | llvm-svn: 313262
* [mips] Pick the right variant of DINS upfront and enable target instruction ↵Simon Dardis2017-09-148-44/+119
| | | | | | | | | | | | | | | | | | | | | | | | | verification This patch complements D16810 "[mips] Make isel select the correct DEXT variant up front.". Now ISel picks the right variant of DINS, so now there is no need to replace DINS with the appropriate variant during MipsMCCodeEmitter::encodeInstruction(). This patch also enables target specific instruction verification for ins, dins, dinsm, dinsu, ext, dext, dextm, dextu. These instructions have constraints that are checked when generating MipsISD::Ins and MipsISD::Ext nodes, but these constraints are not checked during instruction selection. Adding machine verification should catch outstanding cases. Finally, correct a bug that instruction verification uncovered, where the position operand of a DINSU generated during lowering was being silently and accidently corrected to the correct value. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D34809 llvm-svn: 313254
* [mips] correct operand range for DINSM instructionPetar Jovanovic2017-09-131-1/+1
| | | | | | | | | | | | | This patch corrects the definition of the DINSM instruction. Specification for DINSM instruction for Mips64 says that size operand should be 2 <= size <= 64, but it is defined as uimm5_inssize_plus1 which gives range of 1 .. 32. Patch by Aleksandar Beserminji. Differential Revision: https://reviews.llvm.org/D37683 llvm-svn: 313149
* [mips] handle UImm16_AltRelaxed match typePetar Jovanovic2017-09-121-0/+1
| | | | | | | | | | | | | Currently, UImm16_AltRelaxed match type is not handled in MatchAndEmitInstruction() function, which may result in llvm_unreachable() behavior. This patch adds necessary case for this match type. Patch by Aleksandar Beserminji. Differential Revision: https://reviews.llvm.org/D37682 llvm-svn: 313077
* [mips][microMIPS] add lapc instructionPetar Jovanovic2017-09-112-0/+6
| | | | | | | | | | Implement LAPC instruction for mips32r6, mips64r6 and micromips32r6. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D35984 llvm-svn: 312934
* [mips] Use RegisterMCAsmBackend to register all MIPS asm backends. NFCSimon Atanasyan2017-09-075-81/+28
| | | | | | | | | | | | | This change converts the `MipsAsmBackend` constructor to the "standard" form. It makes possible to use `RegisterMCAsmBackend` for the backends registrations. Now we pass `Triple` instance to the `MipsAsmBackend` ctor and deduce all required options like endianness and bitness from the triple. We still need to implement explicit ABI checking for providing correct options to backends. Differential revision: https://reviews.llvm.org/D37519 llvm-svn: 312720
* [MIPS] Add support to match more patterns for BBIT instructionStrahinja Petrovic2017-08-301-0/+15
| | | | | | | | | | This patch supports one more pattern for bbit0 and bbit1 instructions, CBranchBitNum class is expanded so it can take 32 bit immidate. Differential Revision: https://reviews.llvm.org/D36222 llvm-svn: 312111
* [mips] Generate NMADD and NMSUB instructions when fneg node is presentPetar Jovanovic2017-08-272-0/+20
| | | | | | | | | | | | This patch enables generation of NMADD and NMSUB instructions when fneg node is present. These instructions are currently only generated if fsub node is present. Patch by Stanislav Ocovaj. Differential Revision: https://reviews.llvm.org/D34507 llvm-svn: 311862
* [mips] Follow up comments on r310460Simon Dardis2017-08-181-2/+1
| | | | | | Use dblaikie's suggestion of cast<> instead of a seperate assert. llvm-svn: 311160
* [mips] Handle variables with an explicit section and interactions with ↵Simon Dardis2017-08-161-0/+16
| | | | | | | | | | | | | | | | | | .sdata, .sbss If a variable has an explicit section such as .sdata or .sbss, it is placed in that section and accessed in a gp relative manner. This overrides the global -G setting. Otherwise if a variable has a explicit section attached to it, such as '.rodata' or '.mysection', it is not placed in the small data section. This also overrides the global -G setting. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D36616 llvm-svn: 311001
* [MIPS] Implement support for -mstack-alignment.John Baldwin2017-08-146-16/+32
| | | | | | | | | | | | | | | | | | | | | Summary: This is modeled on the implementation for x86 which stores the command line option in a 'StackAlignOverride' field in MipsSubtarget and then uses this to compute a 'stackAlignment' value in MipsSubtarget::initializeSubtargetDependencies. The stackAlignment() method in MipsSubTarget is renamed to getStackAlignment() and returns the computed 'stackAlignment'. Reviewers: sdardis Reviewed By: sdardis Subscribers: llvm-commits, arichardson Differential Revision: https://reviews.llvm.org/D35874 llvm-svn: 310891
* Revert "Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""Simon Dardis2017-08-147-375/+1
| | | | | | | This reverts r310834. It didn't pacify the buildbot, FileCheck is still crashing. llvm-svn: 310854
* Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-08-147-1/+375
| | | | | | | | | | | | | | | | | | | | This adjusts the tests to hopfully pacify the llvm-clang-x86_64-expensive-checks-win buildbot. Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 310834
* [MIPS] Use ABI to determine stack alignment.John Baldwin2017-08-111-1/+3
| | | | | | | | | | | | | | | | Summary: The stack alignment depends on the ABI (16 bytes for N32 and N64 and 8 bytes for O32), not the CPU type. Reviewers: sdardis Reviewed By: sdardis Subscribers: atanasyan, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D36326 llvm-svn: 310768
* [mips] clang-format MipsSubtarget.cpp.John Baldwin2017-08-111-3/+3
| | | | | | This only fixes a few things and serves as my initial test commit. llvm-svn: 310742
* [mips] Lift the assertion on the types that can be used with MipsGPRelSimon Dardis2017-08-114-10/+27
| | | | | | | | | | | | | | | | Post commit review of rL308619 highlighted the need for handling N64 with -fno-pic. Testing reveale a stale assert when generating a GP relative addressing mode. This patch removes that assert and adds the necessary patterns for MIPS64 to perform gp relative addressing with -fno-pic (and the implicit -mno-abicalls + -mgpopt). Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D36472 llvm-svn: 310713
* Add "Restored" flag to CalleeSavedInfoKrzysztof Parzyszek2017-08-102-2/+2
| | | | | | | | | | | The liveness-tracking code assumes that the registers that were saved in the function's prolog are live outside of the function. Specifically, that registers that were saved are also live-on-exit from the function. This isn't always the case as illustrated by the LR register on ARM. Differential Revision: https://reviews.llvm.org/D36160 llvm-svn: 310619
* [mips][microMIPS] Extending size reduction pass with XOR16Zoran Jovanovic2017-08-101-5/+43
| | | | | | | | | | Author: milena.vujosevic.janicic Reviewers: sdardis The patch extends size reduction pass for MicroMIPS. XOR instruction is transformed into 16-bit instruction XOR16, if possible. Differential Revision: https://reviews.llvm.org/D34239 llvm-svn: 310579
* [mips] PR34083 - Wimplicit-fallthrough warning in MipsAsmParser.cppSimon Dardis2017-08-091-6/+7
| | | | | | | | | | | | Assert that a binary expression is actually a binary expression, rather than potientially incorrectly attempting to handle it as a unary expression. This resolves PR34083. Thanks to Simonn Pilgrim for reporting the issue! llvm-svn: 310460
* [mips][microMIPS] Extending size reduction pass with ADDIUSP and ADDIUR1SPZoran Jovanovic2017-08-041-14/+101
| | | | | | | | | | | | Author: milena.vujosevic.janicic The patch extends size reduction pass for MicroMIPS. The following instructions are examined and transformed, if possible: ADDIU instruction is transformed into 16-bit instruction ADDIUSP ADDIU instruction is transformed into 16-bit instruction ADDIUR1SP Usage of u_int64_t replaced by uint64_t to avoid issues because of which previous patch version was reverted: Differential Revision: https://reviews.llvm.org/D34511 llvm-svn: 310044
* [Mips] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-08-0326-290/+436
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 309993
* Delete Default and JITDefault code modelsRafael Espindola2017-08-032-17/+24
| | | | | | | | | | | | | | | IMHO it is an antipattern to have a enum value that is Default. At any given piece of code it is not clear if we have to handle Default or if has already been mapped to a concrete value. In this case in particular, only the target can do the mapping and it is nice to make sure it is always done. This deletes the two default enum values of CodeModel and uses an explicit Optional<CodeModel> when it is possible that it is unspecified. llvm-svn: 309911
* [Mips] Fix for BBIT octeon instructionStrahinja Petrovic2017-08-011-1/+7
| | | | | | | | | | | This patch enables control flow optimization for variations of BBIT instruction. In this case optimization removes unnecessary branch after BBIT instruction. Differential Revision: https://reviews.llvm.org/D35359 llvm-svn: 309679
* Change CallLoweringInfo::CS to be an ImmutableCallSite instead of a pointer. ↵Peter Collingbourne2017-07-261-1/+1
| | | | | | | | NFCI. This was a use-after-free waiting to happen. llvm-svn: 309159
* TargetLowering: Change isShuffleMaskLegal's mask argument type to ↵Zvi Rackover2017-07-261-2/+1
| | | | | | | | | | | | | ArrayRef<int>. NFCI. Changing mask argument type from const SmallVectorImpl<int>& to ArrayRef<int>. This came up in D35700 where a mask is received as an ArrayRef<int> and we want to pass it to TargetLowering::isShuffleMaskLegal(). Also saves a few lines of code. llvm-svn: 309085
* [mips] Support -membedded-data and fix a related bugSimon Dardis2017-07-211-2/+15
| | | | | | | | | | | | -membedded-data changes the location of constant data from the .sdata to the .rodata section. Previously it was (incorrectly) always located in the .rodata section. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D35686 llvm-svn: 308758
* [mips] Enable IAS by default for Android MIPS64Petar Jovanovic2017-07-211-0/+4
| | | | | | | | | Follow up to r306280 in Clang. Enable IAS by default for Android MIPS64 (uses N64 ABI). Differential Revision: https://reviews.llvm.org/D35482 llvm-svn: 308742
* [SystemZ, LoopStrengthReduce]Jonas Paulsson2017-07-212-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes LSR generate better code for SystemZ in the cases of memory intrinsics, Load->Store pairs or comparison of immediate with memory. In order to achieve this, the following common code changes were made: * New TTI hook: LSRWithInstrQueries(), which defaults to false. Controls if LSR should do instruction-based addressing evaluations by calling isLegalAddressingMode() with the Instruction pointers. * In LoopStrengthReduce: handle address operands of memset, memmove and memcpy as address uses, and call isFoldableMemAccessOffset() for any LSRUse::Address, not just loads or stores. SystemZ changes: * isLSRCostLess() implemented with Insns first, and without ImmCost. * New function supportedAddressingMode() that is a helper for TTI methods looking at Instructions passed via pointers. Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D35262 https://reviews.llvm.org/D35049 llvm-svn: 308729
* Reland r308585Stefan Maksimovic2017-07-208-42/+71
| | | | | | | | Builder clang-x86_64-linux-abi-test apparently failed due to a spurious error unrelated to the changes r308585 introduced. llvm-svn: 308612
* [mips] Support `long_call/far/near` attributes passed by front-endSimon Atanasyan2017-07-201-9/+24
| | | | | | | | | This patch adds handling of the `long_call`, `far`, and `near` attributes passed by front-end. The patch depends on D35479. Differential revision: https://reviews.llvm.org/D35480. llvm-svn: 308606
* Revert r308585Stefan Maksimovic2017-07-208-71/+42
| | | | | | Builder clang-x86_64-linux-abi-test seems to fail after this change llvm-svn: 308597
* [mips] Fix fp select machine verifier errorsStefan Maksimovic2017-07-208-42/+71
| | | | | | | | | | | | | | | | | Introduced FSELECT node necesary when lowering ISD::SELECT which has i32, f64, f64 as its operands. SEL_D instruction required that its output and first operand of a SELECT node, which it used, have matching types. MTC1_D64 node introduced to aid FSELECT lowering. This fixes machine verifier errors on following tests: CodeGen/Mips/llvm-ir/select-dbl.ll CodeGen/Mips/llvm-ir/select-flt.ll CodeGen/Mips/select.ll Differential Revision: https://reviews.llvm.org/D35408 llvm-svn: 308595
* [mips] Alter register classes for MSA pseudo f16 instructionsStefan Maksimovic2017-07-182-4/+32
| | | | | | | | | | | This change introduces additional machine instructions in functions dealing with the expansion of msa pseudo f16 instructions due to register classes being inappropriate when checked with machine verifier. Differential Revision: https://reviews.llvm.org/D34276 llvm-svn: 308301
* [mips] Handle the `long-calls` feature flags in the MIPS backendSimon Atanasyan2017-07-153-0/+22
| | | | | | | | | | If the `long-calls` feature flags is enabled, disable use of the `jal` instruction. Instead of that call a function by by first loading its address into a register, and then using the contents of that register. Differential revision: https://reviews.llvm.org/D35168 llvm-svn: 308087
* Revert "Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""Simon Dardis2017-07-146-372/+0
| | | | | | | | | FileCheck is crashing on in the input file, so reverting again while I investigate. This reverts r308023. llvm-svn: 308030
* Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""Simon Dardis2017-07-146-0/+372
| | | | | | | | | | | | | | | | | | | | | | | | Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 The last version of this patch broke one of the expensive checks buildbots, this version changes the failing test/MC/Mips/mt/invalid.s and other invalid tests to write the errors to a file and run FileCheck on that, rather than relying on the 'not llvm-mc ... <%s 2>&1 | Filecheck %s' idiom. Hopefully this will sarisfy the buildbot. llvm-svn: 308023
* Reverting commit 308011.Zoran Jovanovic2017-07-141-101/+14
| | | | llvm-svn: 308017
* [mips][microMIPS] Extending size reduction pass with ADDIUSP and ADDIUR1SPZoran Jovanovic2017-07-141-14/+101
| | | | | | | | | | | | | | Author: milena.vujosevic.janicic Reviewers: sdardis The patch extends size reduction pass for MicroMIPS. The following instructions are examined and transformed, if possible: ADDIU instruction is transformed into 16-bit instruction ADDIUSP ADDIU instruction is transformed into 16-bit instruction ADDIUR1SP Function InRange is changed to avoid left shifting of negative values, since that caused some sanitizer tests to fail (so the previous patch Differential Revision: https://reviews.llvm.org/D34511 llvm-svn: 308011
* Revert "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-07-136-372/+0
| | | | | | | This reverts r307836, it broke one of the buildbots. Reverting while I investigate. llvm-svn: 307939
* Reland "[mips] Fix multiprecision arithmetic."Simon Dardis2017-07-134-226/+184
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
* [mips][mt][6/7] Add support for mftr, mttr instructions.Simon Dardis2017-07-126-0/+372
| | | | | | | | | | | | | | | | | Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 307836
* [mips][mt][5/7] Add support for fork and yield instructions.Simon Dardis2017-07-124-2/+65
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35252 llvm-svn: 307808
* [mips][mt][4/7] Add IAS support for dvpe, evpe instructions.Simon Dardis2017-07-124-5/+28
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35251 llvm-svn: 307793
* [mips][mt] Add missing files from last commitSimon Dardis2017-07-122-0/+104
| | | | llvm-svn: 307779
* [mips][mt][3/7] Add IAS support for emt, dmt instructions.Simon Dardis2017-07-124-2/+21
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35250 llvm-svn: 307774
* Fully fix the movw/movt addend.Rafael Espindola2017-07-112-2/+2
| | | | | | | | | | The issue is not if the value is pcrel. It is whether we have a relocation or not. If we have a relocation, the static linker will select the upper bits. If we don't have a relocation, we have to do it. llvm-svn: 307730
* [mips][mt] Correct spelling error in comment. NFCI.Simon Dardis2017-07-111-1/+1
| | | | llvm-svn: 307717
* [mips][mt][2/7] Implement .module and .set directives for the MT ASE.Simon Dardis2017-07-113-0/+82
| | | | | | | | | | | | This patch implements the .module and .set directives for the MT ASE, notably that .module sets the relevant flags in .MIPS.abiflags and .set doesn't. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35249 llvm-svn: 307716
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