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* Fix typo.Akira Hatanaka2011-11-121-1/+1
| | | | llvm-svn: 144453
* Implement Mips64's handling of byval arguments in LowerCall.Akira Hatanaka2011-11-121-12/+100
| | | | llvm-svn: 144452
* Implement Mips64's handling of byval arguments in LowerFormalArguments.Akira Hatanaka2011-11-121-18/+60
| | | | llvm-svn: 144449
* 64-bit arbitrary immediate pattern.Akira Hatanaka2011-11-121-0/+4
| | | | llvm-svn: 144448
* Function for handling byval arguments.Akira Hatanaka2011-11-122-4/+43
| | | | llvm-svn: 144447
* build: Attempt to rectify inconsistencies between CMake and LLVMBuild ↵Daniel Dunbar2011-11-121-1/+1
| | | | | | | | versions of explicit dependencies. - The hope is that we have a tool/test to verify these are accurate (and tight) soon. llvm-svn: 144444
* CMake: Fix CMake build for new Mips tblgen file.Daniel Dunbar2011-11-111-0/+1
| | | | llvm-svn: 144423
* Mips MC object code emission improvements:Bruno Cardoso Lopes2011-11-1113-130/+475
| | | | | | | | | | "With this patch we can now generate runnable Mips code through LLVM direct object emission. We have run numerous simple programs, both C and C++ and with -O0 and -O3 from the output. The code is not production ready, but quite useful for experimentation." Patch and message by Jack Carter llvm-svn: 144414
* Do not try to detect DAG combine patterns for integer multiply-add/sub if valueAkira Hatanaka2011-11-111-2/+4
| | | | | | | type is not i32. MIPS does not have 64-bit integer multiply-add/sub instructions. llvm-svn: 144373
* 64-bit atomic instructions.Akira Hatanaka2011-11-113-64/+194
| | | | llvm-svn: 144372
* Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64.Akira Hatanaka2011-11-111-1/+2
| | | | llvm-svn: 144371
* Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC.Akira Hatanaka2011-11-113-12/+27
| | | | llvm-svn: 144370
* 64-bit versions of jal, jalr and bal.Akira Hatanaka2011-11-112-0/+27
| | | | llvm-svn: 144368
* Emit Mips64's sequence of instructions that set global register in prologue.Akira Hatanaka2011-11-111-1/+21
| | | | llvm-svn: 144367
* Fix printing of MCSymbolRegExpr. Needs three closing parentheses forAkira Hatanaka2011-11-111-1/+4
| | | | | | VK_Mips_GPOFF_HI/LO. llvm-svn: 144366
* LLVMBuild: Add explicit information on whether targets define an assembly ↵Daniel Dunbar2011-11-111-0/+1
| | | | | | printer, assembly parser, or disassembler. llvm-svn: 144344
* llvm-build: Add --native-target and --enable-targets options, and add logic toDaniel Dunbar2011-11-101-1/+0
| | | | | | | | | | handle defining the "magic" target related components (like native, nativecodegen, and engine). - We still require these components to be in the project (currently in lib/Target) so that we have a place to document them and hopefully make it more obvious that they are "magic". llvm-svn: 144253
* llvm-build: Add an explicit component type to represent targets.Daniel Dunbar2011-11-101-1/+2
| | | | | | - Gives us a place to hang target specific metadata (like whether the target has a JIT). llvm-svn: 144250
* Properly handle Mips MC relocations and lower cpload and cprestore macros to ↵Bruno Cardoso Lopes2011-11-084-45/+191
| | | | | | | | MCInsts. Patch by Jack Carter. llvm-svn: 144139
* Added invariant field to the DAG.getLoad method and changed all calls.Pete Cooper2011-11-081-9/+9
| | | | | | When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses llvm-svn: 144100
* This patch handles unaligned loads and stores in Mips JIT. Mips backendBruno Cardoso Lopes2011-11-082-6/+148
| | | | | | | | | | | | implements unaligned loads and stores with assembler macro-instructions ulw, usw, ulh, ulhu, ush, and this patch emits corresponding instructions instead of these macros. Since each unaligned load/store is expanded into two corresponding loads/stores where offset for second load/store is modified by +3 (for words) or +1 (for halfwords). Patch by Petar Jovanovic and Sasa Stankovic. llvm-svn: 144081
* Various Mips64 floating point instruction patterns.Akira Hatanaka2011-11-071-3/+18
| | | | llvm-svn: 144019
* Add definition of the base class for floating point comparison instructionsAkira Hatanaka2011-11-071-8/+8
| | | | | | and add Mips64's version too. llvm-svn: 144018
* Add code needed for copying between 64-bit integer and floating pointerAkira Hatanaka2011-11-071-0/+6
| | | | | | registers. llvm-svn: 144017
* Add definitions of 64-bit instructions which move data between integer andAkira Hatanaka2011-11-071-0/+8
| | | | | | floating pointer registers. llvm-svn: 144016
* Add definition of 64-bit load upper immediate.Akira Hatanaka2011-11-072-3/+4
| | | | llvm-svn: 143994
* Include RegSaveAreaSize in the computation of stack size.Akira Hatanaka2011-11-071-0/+1
| | | | llvm-svn: 143993
* Define functions that get or set the size of area on callee's stack frame whichAkira Hatanaka2011-11-071-1/+10
| | | | | | is used to save va_arg or byval arguments passed in registers. llvm-svn: 143992
* Use array_lengthof to compute the number of iterations of a loop.Akira Hatanaka2011-11-071-6/+6
| | | | llvm-svn: 143991
* Fix patterns for unaligned 32-bit load. DSLL32 or DSRL32 should be emittedAkira Hatanaka2011-11-071-2/+2
| | | | | | when shift amount is larger than 32. llvm-svn: 143990
* Make the type of shift amount i32 in order to reduce the number of shiftAkira Hatanaka2011-11-073-5/+7
| | | | | | instruction definitions. llvm-svn: 143989
* Add 64-bit to 32-bit trunc pattern.Akira Hatanaka2011-11-071-0/+5
| | | | llvm-svn: 143988
* Replace (Lower|Upper)caseString in favor of StringRef's newest methods.Benjamin Kramer2011-11-062-7/+5
| | | | llvm-svn: 143891
* build/cmake: Use tblgen macro directly instead of llvm_tablegen, which justDaniel Dunbar2011-11-041-7/+7
| | | | | | added a layer of indirection with no value (not even conciseness). llvm-svn: 143727
* build: Add initial cut at LLVMBuild.txt files.Daniel Dunbar2011-11-034-0/+102
| | | | llvm-svn: 143634
* Make changes necessary in LowerFormalArguments to support Mips64.Akira Hatanaka2011-10-281-17/+17
| | | | llvm-svn: 143218
* Make changes necessary in LowerCall to support Mips64.Akira Hatanaka2011-10-281-25/+38
| | | | llvm-svn: 143217
* Add variable IsO32 to MipsTargetLowering.Akira Hatanaka2011-10-282-10/+11
| | | | llvm-svn: 143213
* Corrects previously incorrect $sp change in MipsCompilationCallback.Bruno Cardoso Lopes2011-10-251-7/+7
| | | | | | | | The address for $sp, and addresses for sdc1/ldc1 must be 8-byte aligned Patch by Petar Jovanovic. llvm-svn: 142930
* Final patch that completes old JIT support for Mips:Bruno Cardoso Lopes2011-10-187-91/+173
| | | | | | | | | | | | | | | | -Fix binary codes and rename operands in .td files so that automatically generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct encoding for instructions. -Define new class FMem for instructions that access memory. -Define new class FFRGPR for instructions that move data between GPR and FPU general and control registers. -Define custom encoder methods for memory operands, and also for size operands of ext and ins instructions. -Only static relocation model is currently implemented. Patch by Sasa Stankovic llvm-svn: 142378
* Coding style cleanups. No functionality change.Bill Wendling2011-10-181-6/+5
| | | | llvm-svn: 142341
* Fix misc warnings. Patch by Joe Abbey.Eli Friedman2011-10-181-2/+0
| | | | llvm-svn: 142332
* Add definitions of conditional moves with 64-bit operands. Comment out code forAkira Hatanaka2011-10-173-75/+130
| | | | | | | expanding conditional moves, which is not needed since architectures that lack support for conditional moves have been removed. llvm-svn: 142226
* Move class and instruction definitions for conditional moves to a seperate file.Akira Hatanaka2011-10-174-106/+112
| | | | llvm-svn: 142220
* Revert change made in r142205.Akira Hatanaka2011-10-171-2/+2
| | | | llvm-svn: 142217
* Redefine count-leading 0s and 1s instructions.Akira Hatanaka2011-10-172-20/+17
| | | | llvm-svn: 142216
* Redefine mfhi/lo and mthi/lo instructions.Akira Hatanaka2011-10-172-35/+16
| | | | llvm-svn: 142214
* Redefine multiply and divide instructions.Akira Hatanaka2011-10-172-25/+26
| | | | llvm-svn: 142211
* Add definition of a base class for logical shift/rotate instructions with twoAkira Hatanaka2011-10-172-20/+12
| | | | | | source registers and redefine 32-bit and 64-bit instructions. llvm-svn: 142210
* Add definition of a base class for logical shift/rotate immediate instructionsAkira Hatanaka2011-10-172-27/+33
| | | | | | and have 32-bit and 64-bit instructions derive from it. llvm-svn: 142207
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