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* Reverted revisions 221351, 221352 and 221353.Zoran Jovanovic2014-11-056-99/+11
| | | | llvm-svn: 221354
* [mips][microMIPS] Implement CodeGen support for ANDI16 instructionZoran Jovanovic2014-11-052-2/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D5797 llvm-svn: 221353
* [mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructionsZoran Jovanovic2014-11-052-9/+22
| | | | | | Differential Revision: http://reviews.llvm.org/D5933 llvm-svn: 221352
* [mips][microMIPS] Implement ANDI16 instructionZoran Jovanovic2014-11-055-0/+64
| | | | | | Differential Revision: http://reviews.llvm.org/D5163 llvm-svn: 221351
* Revert "[mips] Add names and tests for the hardware registers"Rafael Espindola2014-11-042-39/+2
| | | | | | | | | | | | | This reverts commit r221299. The tests LLVM :: MC/Disassembler/Mips/mips32.txt LLVM :: MC/Disassembler/Mips/mips32_le.txt were failing. llvm-svn: 221307
* [mips] Move COP2 & COP3 load/store instructions from MipsInstrFPU.td to ↵Vasileios Kalintiris2014-11-042-56/+54
| | | | | | | | | | | | | | MipsInstrInfo.td. NFC. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5843 llvm-svn: 221300
* [mips] Add names and tests for the hardware registersVasileios Kalintiris2014-11-042-2/+39
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5763 llvm-svn: 221299
* [mips] Improve support for the .set mips16/nomips16 assembler directives.Toma Tabacu2014-11-041-6/+22
| | | | | | | | | | | | | | | | | | | Summary: Appropriately set/clear the FeatureBit for Mips16 when these assembler directives are used and also emit ".set nomips16" (previously, only ".set mips16" was being emitted). These improvements allow for better testing of the .cpload/.cprestore assembler directives (which are not supposed to work when Mips16 is enabled). Test Plan: The test is bare-bones because there are no MC tests for Mips16 instructions (there's only one, which checks that the Mips16 ELF header flag gets set), and that suggests to me that it has not been implemented yet in the IAS. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5462 llvm-svn: 221277
* [mips] Remove unused prototype and variable. NFC.Daniel Sanders2014-11-032-5/+0
| | | | llvm-svn: 221146
* Re-commit r221056 and others with fix, "[mips] Move F128 argument handling ↵Daniel Sanders2014-11-0210-175/+255
| | | | | | | | | into MipsCCState as we did for returns. NFC." sret arguments can never originate from an f128 argument so we detect sret arguments and push false into OriginalArgWasF128. llvm-svn: 221102
* Revert r221056 and others, "[mips] Move F128 argument handling into ↵NAKAMURA Takumi2014-11-0210-246/+175
| | | | | | | | | | | | | MipsCCState as we did for returns. NFC." r221056 "[mips] Move F128 argument handling into MipsCCState as we did for returns. NFC." r221058 "[mips] Fix unused variable warning introduced in r221056" r221059 "[mips] Move all ByVal handling into CCState and tablegen-erated code. NFC." r221061 "Renamed CCState members that appear to misspell 'Processed' as 'Proceed'. NFC." It cuased an undefined behavior in LLVM :: CodeGen/Mips/return-vector.ll. llvm-svn: 221081
* Renamed CCState members that appear to misspell 'Processed' as 'Proceed'. NFC.Daniel Sanders2014-11-011-2/+2
| | | | | | | | | | | | Reviewers: rnk Reviewed By: rnk Subscribers: rnk, llvm-commits Differential Revision: http://reviews.llvm.org/D5978 llvm-svn: 221061
* [mips] Move all ByVal handling into CCState and tablegen-erated code. NFC.Daniel Sanders2014-11-0110-148/+157
| | | | | | | | | | | | | | | | | Summary: CCState already contains a byval implementation that is very similar to the Mips custom code. This patch merges the custom code into the existing common code and tablegen-erated code. Reviewers: vmedic Reviewed By: vmedic Subscribers: rnk, llvm-commits Differential Revision: http://reviews.llvm.org/D5977 llvm-svn: 221059
* [mips] Fix unused variable warning introduced in r221056Daniel Sanders2014-11-011-1/+0
| | | | llvm-svn: 221058
* [mips] Remove ByValArgInfo::Address in favour of ↵Daniel Sanders2014-11-012-28/+26
| | | | | | | | | | | | | | | | CCValAssign::getMemLocOffset(). NFC. Summary: ByValArgInfo is practically the same as CCState::ByValInfo now. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5976 llvm-svn: 221057
* [mips] Move F128 argument handling into MipsCCState as we did for returns. NFC.Daniel Sanders2014-11-013-27/+90
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: There are a couple more changes to make before analyzeFormalArguments can be merged into the standard AnalyzeFormalArguments. I've had to temporarily poke a couple holes in MipsCCState's encapsulation to save having to make all the required changes for this merge all at once*. These will be removed shortly. * We must merge our ByVal argument handling with the implementation in CCState. This will be done over the next three patches, then the fourth will merge analyzeFormalArguments with AnalyzeFormalArguments. Depends on D5967 Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5969 llvm-svn: 221056
* [mips] Remove MipsCC::CCInfo. NFC.Daniel Sanders2014-11-012-42/+41
| | | | | | | | | | | | | | | | | | | Summary: It's now passed in as an argument to functions that need it. Eventually this argument will be replaced by the 'this' pointer for a MipsCCState object. Depends on D5966 Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5967 llvm-svn: 221054
* [mips] Removed MipsCC::fixedArgFn(). NFCDaniel Sanders2014-11-012-29/+18
| | | | | | | | | | | | | | | | | | | Summary: There is one remaining trace of it in MipsCC::analyzeCallOperands() where Mips16 might override the calling convention. This will moved into tablegen-erated code later. Depends on D5965 Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5966 llvm-svn: 221053
* [tablegen] Add CustomCallingConv and use it to tablegen-erate the outermost ↵Daniel Sanders2014-11-013-17/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | parts of the Mips O32 implementation Summary: CustomCallingConv is simply a CallingConv that tablegen should not generate the implementation for. It allows regular CallingConv's to delegate to these custom functions. This is (currently) necessary for Mips and we cannot use CCCustom without having to adapt to the different API that CCCustom uses. This brings us a bit closer to being able to remove MipsCC::analyzeCallOperands and MipsCC::analyzeFormalArguments in favour of the common implementation. No functional change to the targets. Depends on D3341 Reviewers: vmedic Reviewed By: vmedic Subscribers: vmedic, llvm-commits Differential Revision: http://reviews.llvm.org/D5965 llvm-svn: 221052
* Revert r221048 - Test commitDaniel Sanders2014-11-011-1/+0
| | | | | | | It seems I can't commit unless $DBUS_SESSION_BUS_ADDRESS is set correctly and it is not set for ssh sessions. llvm-svn: 221049
* Test commitDaniel Sanders2014-11-011-0/+1
| | | | | | Added some whitespace to debug some authentication issues I'm having. llvm-svn: 221048
* [mips] Replace MipsABIEnum with a MipsABIInfo class.Daniel Sanders2014-10-247-32/+70
| | | | | | | | | | | | | | | | | | | | | Summary: No functional change yet, it's just an object replacement for an enum. It will allow us to gather ABI information in a single place so that we can start testing for properties of the ABI's instead of the ABI itself. For example we will eventually be able to use: ABI.MinStackAlignmentInBytes() instead of: (isABI_N32() || isABI_N64()) ? 16 : 8 which is clearer and more maintainable. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3341 llvm-svn: 220568
* [mips] Fix >80-column lineDaniel Sanders2014-10-241-1/+2
| | | | llvm-svn: 220564
* [mips] Remove redundant code in RetCC_MipsN. NFC.Daniel Sanders2014-10-241-3/+0
| | | | | | | | | | | | | | | | Summary: i32 is always promoted to i64 so it no longer makes sense to assign i32 to registers. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5964 llvm-svn: 220561
* [mips] For N32/N64, structs must be passed in the upper bits of a register.Daniel Sanders2014-10-241-2/+2
| | | | | | | | | | | | | | | | | | Summary: Most structs were fixed by r218451 but those of between >32-bits and <64-bits remained broken since they were not marked with [ASZ]ExtUpper. This patch fixes the remaining cases by using CCPromoteToUpperBitsInType<i64> on i64's in addition to i32 and smaller. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5963 llvm-svn: 220556
* [mips][microMIPS] Implement ADDIUR1SP instructionZoran Jovanovic2014-10-235-0/+49
| | | | | | Differential Revision: http://reviews.llvm.org/D5153 llvm-svn: 220477
* ps][microMIPS] Implement ADDIUR2 instructionZoran Jovanovic2014-10-235-0/+53
| | | | | | Differential Revision: http://reviews.llvm.org/D5151 llvm-svn: 220476
* ps][microMIPS] Implement LI16 instructionZoran Jovanovic2014-10-233-0/+31
| | | | | | Differential Revision: http://reviews.llvm.org/D5149 llvm-svn: 220475
* [mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructionsZoran Jovanovic2014-10-235-0/+54
| | | | | | Differential Revision: http://reviews.llvm.org/D5774 llvm-svn: 220474
* [mips][microMIPS] Implement ADDU16 and SUBU16 instructionsZoran Jovanovic2014-10-212-0/+27
| | | | | | Differential Revision: http://reviews.llvm.org/D5118 llvm-svn: 220276
* [mips][microMIPS] Implement AND16, NOT16, OR16 and XOR16 instructionsZoran Jovanovic2014-10-212-0/+34
| | | | | | Differential Revision: http://reviews.llvm.org/D5117 llvm-svn: 220275
* [mips][microMIPS] Implement microMIPS 16-bit instructions registersZoran Jovanovic2014-10-213-0/+46
| | | | | | Differential Revision: http://reviews.llvm.org/D5116 llvm-svn: 220273
* Mips: Only set divrem i64 to custom on 64bitJan Vesely2014-10-171-2/+2
| | | | | | Reviewed-by: Daniel Sanders <daniel.sanders@imgtec.com> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 220046
* [mips] Add support for COP1's Branch-On-Cond-Likely instructionsVasileios Kalintiris2014-10-171-2/+10
| | | | | | | | | | | | Summary: Depends on D5782 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5802 llvm-svn: 220042
* [mips] Add support for COP0's Branch-On-Cond-Likely instructionsVasileios Kalintiris2014-10-171-6/+25
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5782 llvm-svn: 220036
* Erase fence insertion from SelectionDAGBuilder.cpp (NFC)Robin Morisset2014-10-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Backends can use setInsertFencesForAtomic to signal to the middle-end that montonic is the only memory ordering they can accept for stores/loads/rmws/cmpxchg. The code lowering those accesses with a stronger ordering to fences + monotonic accesses is currently living in SelectionDAGBuilder.cpp. In this patch I propose moving this logic out of it for several reasons: - There is lots of redundancy to avoid: extremely similar logic already exists in AtomicExpand. - The current code in SelectionDAGBuilder does not use any target-hooks, it does the same transformation for every backend that requires it - As a result it is plain *unsound*, as it was apparently designed for ARM. It happens to mostly work for the other targets because they are extremely conservative, but Power for example had to switch to AtomicExpand to be able to use lwsync safely (see r218331). - Because it produces IR-level fences, it cannot be made sound ! This is noted in the C++11 standard (section 29.3, page 1140): ``` Fences cannot, in general, be used to restore sequential consistency for atomic operations with weaker ordering semantics. ``` It can also be seen by the following example (called IRIW in the litterature): ``` atomic<int> x = y = 0; int r1, r2, r3, r4; Thread 0: x.store(1); Thread 1: y.store(1); Thread 2: r1 = x.load(); r2 = y.load(); Thread 3: r3 = y.load(); r4 = x.load(); ``` r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all seq_cst. But if they are lowered to monotonic accesses, no amount of fences can prevent it.. This patch does three things (I could cut it into parts, but then some of them would not be tested/testable, please tell me if you would prefer that): - it provides a default implementation for emitLeadingFence/emitTrailingFence in terms of IR-level fences, that mimic the original logic of SelectionDAGBuilder. As we saw above, this is unsound, but the best that can be done without knowing the targets well (and there is a comment warning about this risk). - it then switches Mips/Sparc/XCore to use AtomicExpand, relying on this default implementation (that exactly replicates the logic of SelectionDAGBuilder, so no functional change) - it finally erase this logic from SelectionDAGBuilder as it is dead-code. Ideally, each target would define its own override for emitLeading/TrailingFence using target-specific fences, but I do not know the Sparc/Mips/XCore memory model well enough to do this, and they appear to be dealing fine with the ARM-inspired default expansion for now (probably because they are overly conservative, as Power was). If anyone wants to compile fences more agressively on these platforms, the long comment should make it clear why he should first override emitLeading/TrailingFence. Test Plan: make check-all, no functional change Reviewers: jfb, t.p.northover Subscribers: aemerson, llvm-commits Differential Revision: http://reviews.llvm.org/D5474 llvm-svn: 219957
* [mips] Account for endianess when expanding BuildPairF64/ExtractElementF64 ↵Vasileios Kalintiris2014-10-161-1/+4
| | | | | | | | | | | | | | | | | | | | nodes. Summary: In order to support big endian targets for the BuildPairF64 nodes we just need to swap the low/high pair registers. Additionally, for the ExtractElementF64 nodes we have to calculate the correct stack offset with respect to the node's register/operand that we want to extract. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5753 llvm-svn: 219931
* [mips] Marked the DI/EI instruction aliases as MIPS32r2Vasileios Kalintiris2014-10-161-2/+2
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5751 llvm-svn: 219927
* Test commit access: remove extra new line at the end of fileVasileios Kalintiris2014-10-161-1/+0
| | | | llvm-svn: 219925
* Simplify handling of --noexecstack by using getNonexecutableStackSection.Rafael Espindola2014-10-155-15/+8
| | | | llvm-svn: 219799
* Finish getting Mips fast-isel to match up with AArch64 fast-iselReed Kotler2014-10-141-402/+396
| | | | | | | | | | | | | | | | | | | Summary: In order to facilitate use of common code, checking by reviewers of other fast-isel ports, and hopefully to eventually move most of Mips and other fast-isel ports into target independent code, I've tried to get the two implementations to line up. There is no functional code change. Just methods moved in the file to be in the same order as in AArch64. Test Plan: No functional change. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, aemerson, rfuhler Differential Revision: http://reviews.llvm.org/D5692 llvm-svn: 219703
* Make first of several changes to bring up to AArch64 fast-isel styleReed Kotler2014-10-131-179/+204
| | | | | | | | | | | | | | | | | | | | | | | Summary: Make Mips fast-isel track the form of AArch64 where practical. This makes it easier for people to review the code, to borrow similar code, and to see how to eventually move a lot of this target code for fast-isels into target independent code. These are just cosmetic changes. Should be no functional difference. Test Plan: make check test-suite for 4 flavors mips32 r1/r2 , -O0/-O2 Reviewers: dsanders Reviewed By: dsanders Subscribers: aemerson, llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D5595 llvm-svn: 219633
* Add basic conditional branches in mips fast-iselReed Kotler2014-10-111-7/+48
| | | | | | | | | | | | | | | | | | Summary: Implement the most basic form of conditional branches in Mips fast-isel. Test Plan: br1.ll run 4 flavors of test-suite. mips32 r1/r2 and at -O0/O2 Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D5583 llvm-svn: 219556
* [mips] Actually mark that the default case is unreachable as this switchChandler Carruth2014-10-101-1/+1
| | | | | | | | | is over a subset of condition codes. This fixes the -Werror build which warns about use of uninitialized variables in the default case. llvm-svn: 219531
* Implement floating point compare for mips fast-iselReed Kotler2014-10-101-2/+56
| | | | | | | | | | | | | | | | | | Summary: Expand SelectCmp to handle floating point compare Test Plan: fpcmpa.ll run 4 flavors of test-suite, mips32 r1/r2 O0/O2 Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D5567 llvm-svn: 219530
* implement integer compare in mips fast-iselReed Kotler2014-10-101-0/+99
| | | | | | | | | | | | | | | | | | Summary: implement SelectCmp (integer compare ) in mips fast-isel Test Plan: icmpa.ll also ran 4 test-suite flavors mips32 r1/r2 O0/O2 Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, rfuhler, mcrosier Differential Revision: http://reviews.llvm.org/D5566 llvm-svn: 219518
* Implement floating point to integer conversion in mips fast-iselReed Kotler2014-10-101-1/+69
| | | | | | | | | | | | | | | | | | Summary: Add the ability to convert 64 or 32 bit floating point values to integer in mips fast-isel Test Plan: fpintconv.ll ran 4 flavors of test-suite with no errors, misp32 r1/r2 O0/O2 Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, rfuhler, mcrosier Differential Revision: http://reviews.llvm.org/D5562 llvm-svn: 219511
* [mips][microMIPS] Implement ADDIUSP instructionZoran Jovanovic2014-10-105-0/+48
| | | | | | Differential Revision: http://reviews.llvm.org/D5084 llvm-svn: 219500
* [mips][microMIPS] Implement JR16 instructionZoran Jovanovic2014-10-101-0/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D5062 llvm-svn: 219498
* [mips][microMIPS] Implement ADDIUS5 instructionZoran Jovanovic2014-10-103-0/+41
| | | | | | Differential Revision: http://reviews.llvm.org/D5049 llvm-svn: 219495
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