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* Add #include of raw_ostream.h to MipsSEISelLowering.cppHans Wennborg2013-10-301-0/+1
| | | | | | | | Fixing this Windows build error: ..\lib\Target\Mips\MipsSEISelLowering.cpp(997) : error C2027: use of undefined type 'llvm::raw_ostream' llvm-svn: 193696
* [mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related testsDaniel Sanders2013-10-301-8/+29
| | | | llvm-svn: 193695
* [mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from ↵Daniel Sanders2013-10-303-10/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | normal IR (i.e. not intrinsics) Also corrected the definition of the intrinsics for these instructions (the result register is also the first operand), and added intrinsics for bsel and bseli to clang (they already existed in the backend). These four operations are mostly equivalent to bsel, and bseli (the difference is which operand is tied to the result). As a result some of the tests changed as described below. bitwise.ll: - bsel.v test adapted so that the mask is unknown at compile-time. This stops it emitting bmnzi.b instead of the intended bsel.v. - The bseli.b test now tests the right thing. Namely the case when one of the values is an uimm8, rather than when the condition is a uimm8 (which is covered by bmnzi.b) compare.ll: - bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this is the same operation (see MSA.txt). i8.ll - CHECK-DAG-ized test. - bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands because this is the same operation (see MSA.txt). - bseli.b still emits bseli.b though because the immediate makes it distinguishable from bmnzi.b. vec.ll: - CHECK-DAG-ized test. - bmz.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). - bsel.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). llvm-svn: 193693
* [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. ↵Daniel Sanders2013-10-307-27/+163
| | | | | | | | | | | | | | | | | not intrinsics) This required correcting the definition of the bins[lr]i intrinsics because the result is also the first operand. It also required removing the (arbitrary) check for 32-bit immediates in MipsSEDAGToDAGISel::selectVSplat(). Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d because the constant is legalized into a ConstantPool. Similar things can happen with binsri.d with more than 10 bits set in the mask. The resulting code when this happens is correct but not optimal. llvm-svn: 193687
* [mips][msa] Combine binsri-like DAG of AND and OR into equivalent VSELECTDaniel Sanders2013-10-301-0/+108
| | | | | | | | | | | | | | | (or (and $a, $mask), (and $b, $inverse_mask)) => (vselect $mask, $a, $b). where $mask is a constant splat. This allows bitwise operations to make use of bsel. It's also a stepping stone towards matching bins[lr], and bins[lr]i from normal IR. Two sets of similar tests have been added in this commit. The bsel_* functions test the case where binsri cannot be used. The binsr_*_i functions will start to use the binsri instruction in the next commit. llvm-svn: 193682
* [mips] MipsSETargetLowering now reports DAGCombiner changes when using ↵Daniel Sanders2013-10-301-1/+9
| | | | | | | | -debug-only=mips-isel No test since -debug output is intended for developers and not end-users. llvm-svn: 193681
* [mips][msa] Added support for matching splat.[bhw] from normal IR (i.e. not ↵Daniel Sanders2013-10-303-26/+57
| | | | | | | | | | intrinsics) splat.d is implemented but this subtest is currently disabled. This is because it is difficult to match the appropriate IR on MIPS32. There is a patch under review that should help with this so I hope to enable the subtest soon. llvm-svn: 193680
* [mips] Compute stack alignment on the fly.Akira Hatanaka2013-10-303-7/+3
| | | | llvm-svn: 193673
* [mips] Align the stack to 16-bytes for mfp64.Akira Hatanaka2013-10-295-4/+11
| | | | llvm-svn: 193641
* Add a helper getSymbol to AsmPrinter.Rafael Espindola2013-10-292-2/+2
| | | | llvm-svn: 193627
* Support for microMIPS jump instructionsZoran Jovanovic2013-10-2911-21/+138
| | | | llvm-svn: 193623
* The asm printer has a mangler. Use it.Rafael Espindola2013-10-293-7/+4
| | | | llvm-svn: 193618
* [mips] Simplify LowerFormalArguments using getRegClassFor.Akira Hatanaka2013-10-281-15/+2
| | | | | | No functionality change. llvm-svn: 193540
* Prune utf8 chars in comments.NAKAMURA Takumi2013-10-281-3/+3
| | | | llvm-svn: 193512
* Prune trailing linefeeds.NAKAMURA Takumi2013-10-281-1/+0
| | | | llvm-svn: 193511
* Make first substantial checkin of my port of ARM constant islands code to Mips.Reed Kotler2013-10-278-12/+284
| | | | | | | | | | | | Before I just ported the shell of the pass. I've tried to keep everything nearly identical to the ARM version. I think it will be very easy to eventually merge these two and create a new more general pass that other targets can use. I have some improvements I would like to make to allow pools to be shared across functions and some other things. When I'm all done we can think about making a more general pass. More to be ported but the basic mechanism works now almost as good as gcc mips16. llvm-svn: 193509
* Support for microMIPS relocations 1.Zoran Jovanovic2013-10-234-13/+107
| | | | llvm-svn: 193247
* [mips][msa] Direct Object Emission support for the LSA instruction.Matheus Almeida2013-10-232-8/+21
| | | | llvm-svn: 193240
* [mips][msa] Added support for matching fexp2 from normal IR (i.e. not ↵Daniel Sanders2013-10-233-4/+94
| | | | | | intrinsics) llvm-svn: 193239
* [mips][msa] Direct Object Emission support for conditional branches.Matheus Almeida2013-10-222-25/+43
| | | | | | | | | | | | These branches have a 16-bit offset (R_MIPS_PC16). List of conditional branch instructions: bnz.{b,h,w,d} bnz.v bz.{b,h,w,d} bz.v llvm-svn: 193157
* [mips][msa] Direct Object Emission support for LD/ST instructions.Matheus Almeida2013-10-213-24/+56
| | | | llvm-svn: 193082
* [mips][msa] Direct Object Emission support for LDI instructions.Matheus Almeida2013-10-212-8/+13
| | | | llvm-svn: 193081
* [mips][msa] Direct Object Emission support for MOVE.v.Matheus Almeida2013-10-212-2/+7
| | | | llvm-svn: 193080
* [mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. Matheus Almeida2013-10-215-14/+137
| | | | | | | | These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. llvm-svn: 193078
* [mips][msa] Direct Object Emission of SPLAT instruction.Matheus Almeida2013-10-211-12/+16
| | | | llvm-svn: 193077
* [mips][msa] Fix definition of SLD instruction.Matheus Almeida2013-10-212-8/+36
| | | | | | | The second parameter of the SLD intrinsic is the number of columns (GPR) to slide left the source array. llvm-svn: 193076
* [mips][msa] Added lsa instructionDaniel Sanders2013-10-173-0/+30
| | | | llvm-svn: 192895
* [mips][msa] Removed ldx.[bhwd] and stx.[bhwd].Daniel Sanders2013-10-172-59/+0
| | | | | | | | These were present in a previous version of the MSA spec but are not present in the published version. There is no hardware that uses these instructions. llvm-svn: 192888
* [mips][msa] Correct definition order of ftrunc_[su], ftint_[su], and ftq.Daniel Sanders2013-10-171-22/+22
| | | | | | | | Define these three instructions in alphabetical order (like the rest of the file). No functional change. llvm-svn: 192880
* Add a MCAsmInfoELF class and factor some code into it.Rafael Espindola2013-10-162-3/+2
| | | | | | We had a MCAsmInfoCOFF, but no common class for all the ELF MCAsmInfos before. llvm-svn: 192760
* [mips][msa] Added support for build_vector for v4f32 and v2f64.Daniel Sanders2013-10-153-12/+112
| | | | llvm-svn: 192699
* [mips] Define a pseudo instruction which writes to both the lower and higherAkira Hatanaka2013-10-156-15/+51
| | | | | | parts of the accumulators and gets expanded post-RA. llvm-svn: 192667
* [mips] Use predicates to guard instructions using accumulator registers insteadAkira Hatanaka2013-10-152-11/+12
| | | | | | of relying on AddedComplexity. llvm-svn: 192665
* [mips] Rename isel nodes.Akira Hatanaka2013-10-157-33/+31
| | | | llvm-svn: 192663
* [mips] Transfer kill flag to the newly created operand.Akira Hatanaka2013-10-151-1/+5
| | | | llvm-svn: 192662
* [mips] Set HI/LO registers' HWEncoding field.Akira Hatanaka2013-10-151-8/+8
| | | | llvm-svn: 192661
* [mips] Delete unnecessary code.Akira Hatanaka2013-10-151-3/+0
| | | | llvm-svn: 192660
* [mips][msa] Direct Object Emission support for BIT instructions.Matheus Almeida2013-10-142-74/+130
| | | | | | | | | | | | | | | | | | List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
* [mips][msa] Direct Object Emission support for VEC instructions.Matheus Almeida2013-10-142-67/+88
| | | | | | | List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
* [mips][msa] Direct Object Emission of INSVE.{b,h,w,d}.Matheus Almeida2013-10-141-14/+18
| | | | llvm-svn: 192587
* [mips][msa] Direct Object Emission for the majority of the ELM instructions.Matheus Almeida2013-10-142-31/+109
| | | | | | | | | | List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
* [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.Matheus Almeida2013-10-143-14/+175
| | | | | | | | | INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. llvm-svn: 192582
* For Mips16, start to consolidate all forms of 32 bit literal loading so thatReed Kotler2013-10-121-3/+1
| | | | | | they can be better handled and optimized in the Mips16 constant island code. llvm-svn: 192520
* Mips: Disassemble sign-extended 64 bit immediates properly.Benjamin Kramer2013-10-111-1/+3
| | | | | | This doesn't change the meaning of the output, but makes look right. PR17539. llvm-svn: 192483
* This reverts 192447 because of compiler warning generated on darwin build.Matheus Almeida2013-10-113-174/+14
| | | | llvm-svn: 192451
* This reverts r192449 because of compiler warning generated on darwin build.Matheus Almeida2013-10-112-109/+31
| | | | llvm-svn: 192450
* [mips][msa] Direct Object Emission for the majority of the ELM instructions.Matheus Almeida2013-10-112-31/+109
| | | | llvm-svn: 192449
* [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.Matheus Almeida2013-10-113-14/+174
| | | | | | | | INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. llvm-svn: 192447
* [mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from ↵Daniel Sanders2013-10-112-16/+33
| | | | | | normal IR (i.e. not intrinsics) llvm-svn: 192438
* [mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not ↵Daniel Sanders2013-10-112-4/+11
| | | | | | intrinsics) llvm-svn: 192435
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