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* [mips] Range check simm32 and fold MIPS16's imm32 into simm32.Daniel Sanders2016-04-043-39/+67
| | | | | | | | | | | | | | Summary: At this point we should be able to enable IAS by default for O32 without breaking check-all, or recursion. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18439 llvm-svn: 265302
* [mips][microMIPS] Revert commits r264245 and r264248.Zoran Jovanovic2016-04-0211-106/+51
| | | | | | | Commit r264245 was the reason for failing tests in LLVM test suite. Commit r264248 depends on the first one. llvm-svn: 265249
* [MIPS][LLVM-MC] Fix JR encoding for MIPSR6 ISASagar Thakur2016-04-011-1/+1
| | | | | | | | | | Summary: The assembler was picking the wrong JR variant because the pre-R6 one was still enabled at R6. Author: nitesh.jain Reviewers: vkalintiris, dsanders Subscribers: dsanders, llvm-commits, mohit.bhakkad, sagar, bhushan, jaydeep Differential: D18387 llvm-svn: 265134
* Change eliminateCallFramePseudoInstr() to return an iteratorHans Wennborg2016-03-312-3/+3
| | | | | | | | | | | | | | | | | | | | | This will become necessary in a subsequent change to make this method merge adjacent stack adjustments, i.e. it might erase the previous and/or next instruction. It also greatly simplifies the calls to this function from Prolog- EpilogInserter. Previously, that had a bunch of logic to resume iteration after the call; now it just continues with the returned iterator. Note that this changes the behaviour of PEI a little. Previously, it attempted to re-visit the new instruction created by eliminateCallFramePseudoInstr(). That code was added in r36625, but I can't see any reason for it: the new instructions will obviously not be pseudo instructions, they will not have FrameIndex operands, and we have already accounted for the stack adjustment. Differential Revision: http://reviews.llvm.org/D18627 llvm-svn: 265036
* [mips] Range check simm16Daniel Sanders2016-03-314-35/+68
| | | | | | | | | | | | | | | | | | | Summary: There are too many instructions to exhaustively test so addiu and lwc2 are used as representative examples. It should be noted that many memory instructions that should have simm16 range checking do not because it is also necessary to support the macro of the same name which accepts simm32. The range checks for these occur in the macro expansion. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18437 llvm-svn: 265019
* [mips] Range check simm11 and mem_simm11.Daniel Sanders2016-03-312-6/+15
| | | | | | | | | | | | | | | | | | Summary: ldc2/sdc2 now emit slightly worse diagnostics for MIPS-I. The problem is that they don't trigger the custom parser because all the candidates are disabled by feature bits. On all other subtargets, the diagnostics are accurate but are subject to the usual issues of needing to report multiple ways to correct the code (e.g. smaller offset, enable a CPU feature) but only being able to report one error. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18436 llvm-svn: 265018
* [mips] Split mem_msa into range checked mem_simm10 and mem_simm10_lsl[123]Daniel Sanders2016-03-315-65/+99
| | | | | | | | | | | | | | Summary: Also, made test_mi10.s formatting consistent with the majority of the MC tests. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18435 llvm-svn: 265014
* [mips] Range check simm9 and fix a bug this revealed.Daniel Sanders2016-03-314-12/+21
| | | | | | | | | | | | | | Summary: The bug was that microMIPS's [ls]w[lr]e instructions claimed to support a 12-bit offset when it is only 9-bit. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18434 llvm-svn: 265010
* [mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructionsZlatko Buljan2016-03-317-15/+101
| | | | | | Differential Revision: http://reviews.llvm.org/D17334 llvm-svn: 265002
* Silencing warnings from MSVC 2015 Update 2. All of these changes silence ↵Aaron Ballman2016-03-301-1/+1
| | | | | | "C4334 '<<': result of 32-bit shift implicitly converted to 64 bits (was 64-bit shift intended?)". NFC. llvm-svn: 264929
* [mips] Test commit: Mark insertNoop as dead code (NFC)Simon Dardis2016-03-291-0/+1
| | | | llvm-svn: 264728
* [mips] Correct MIPS16 jal/jalx to have uimm26 offsets and add MC layer range ↵Daniel Sanders2016-03-293-5/+9
| | | | | | | | | | | | | | | | checks. NFC. Summary: However, this has no effect at this time because the instructions affected are marked 'isCodeGenOnly=1' and have no alternative for the MC layer. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18179 llvm-svn: 264712
* [MC][mips] Add MipsMCInstrAnalysis class and register it as MC instruction ↵Simon Atanasyan2016-03-241-0/+36
| | | | | | | | | | | | | analyzer The `MipsMCInstrAnalysis` class overrides the `evaluateBranch` method and calculates target addresses for branch and calls instructions. That allows llvm-objdump to print functions' names in branch instructions in the disassemble mode. Differential Revision: http://reviews.llvm.org/D18209 llvm-svn: 264309
* CodeGen: extend RHS when splitting ATOMIC_CMP_SWAP_WITH_SUCCESS.Tim Northover2016-03-241-0/+4
| | | | | | | | | | | | | If the operation's type has been promoted during type legalization, we need to account for the fact that the high bits of the comparison operand are likely unspecified. The LHS is usually zero-extended, but MIPS sign extends it, so we have to be slightly careful. Patch by Simon Dardis. llvm-svn: 264296
* [mips] Range check vsplat_simm5 and vsplat_simm10Daniel Sanders2016-03-242-5/+6
| | | | | | | | | | | | Summary: Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18177 llvm-svn: 264287
* [mips] Range check simm10Daniel Sanders2016-03-243-4/+13
| | | | | | | | | | | | Summary: Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18148 llvm-svn: 264279
* [mips] Tidy up cnMIPS tablegen definitions. NFC.Daniel Sanders2016-03-242-51/+58
| | | | | | | | | | | | | | | | | | | Summary: In particular, make the cnMIPS predicates much more obvious and prefer def ... : ... { let Foo = bar; } over: let Foo = bar in def ... : ...; Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18354 llvm-svn: 264258
* [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, ↵Zlatko Buljan2016-03-249-42/+89
| | | | | | | | DDIVU and DMODU instructions Differential Revision: http://reviews.llvm.org/D17137 llvm-svn: 264248
* [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructionsHrvoje Varga2016-03-249-11/+192
| | | | | | Differential Revision: http://reviews.llvm.org/D17328 llvm-svn: 264246
* [mips][microMIPS] Fix for "Cannot copy registers" assertionHrvoje Varga2016-03-243-9/+17
| | | | | | Differential Revision: http://reviews.llvm.org/D17068 llvm-svn: 264245
* [mips][microMIPS] Delay slot filler modificationsHrvoje Varga2016-03-231-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D18181 llvm-svn: 264147
* [mips] Make simm6 consistent with the rest. NFC.Daniel Sanders2016-03-221-5/+1
| | | | | | | | | | | | Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18147 llvm-svn: 264057
* [mips] Range check simm7.Daniel Sanders2016-03-225-21/+53
| | | | | | | | | | | | | | Summary: Also renamed li_simm7 to li16_imm since it's not a simm7 and has an unusual encoding (it's a uimm7 except that 0x7f represents -1). Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18145 llvm-svn: 264056
* [mips] Range check simm5.Daniel Sanders2016-03-223-3/+7
| | | | | | | | | | | | | | | Summary: We can't check the error message for this one because there's another lw/sw available that covers a larger range. We therefore check the transition between the two sizes. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18144 llvm-svn: 264054
* [mips] Range check vsplat_uimm[1234568].Daniel Sanders2016-03-222-48/+53
| | | | | | | | | | | | Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18143 llvm-svn: 264053
* [mips] Range check uimm4_ptr, remove uimm6_ptr, and use correctly sized ↵Daniel Sanders2016-03-222-42/+52
| | | | | | | | | | | | immediates in MSA copy/insert. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18142 llvm-svn: 264052
* [mips] Use `formatImm` call to print immediate value in the `MipsInstPrinter`Simon Atanasyan2016-03-171-2/+2
| | | | | | | | | That allows, for example, to print hex-formatted immediates using llvm-objdump --print-imm-hex command line option. Differential Revision: http://reviews.llvm.org/D18195 llvm-svn: 263704
* [mips] Eliminate instances of "potentially uninitialised local variable" ↵Scott Egerton2016-03-171-16/+13
| | | | | | | | | | | | | | | | | | warnings, NFC Summary: This should eliminate all occurrences of this within LLVMMipsAsmParser. This patch is in response to http://reviews.llvm.org/D17983. I was unable to reproduce the warnings on my machine so please advise if this fixes the warnings. Reviewers: ariccio, vkalintiris, dsanders Subscribers: dblaikie, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18087 llvm-svn: 263703
* Tweak some atomics functions in preparation for larger changes; NFC.James Y Knight2016-03-162-1/+4
| | | | | | | | | | | | | | | | - Rename getATOMIC to getSYNC, as llvm will soon be able to emit both '__sync' libcalls and '__atomic' libcalls, and this function is for the '__sync' ones. - getInsertFencesForAtomic() has been replaced with shouldInsertFencesForAtomic(Instruction), so that the decision can be made per-instruction. This functionality will be used soon. - emitLeadingFence/emitTrailingFence are no longer called if shouldInsertFencesForAtomic returns false, and thus don't need to check the condition themselves. llvm-svn: 263665
* [Mips] Fix -Wunused-private-field warning after r263444.Chad Rosier2016-03-143-7/+6
| | | | llvm-svn: 263454
* [DAG] use isUndef() ; NFCISanjay Patel2016-03-141-1/+1
| | | | llvm-svn: 263448
* [mips] MIPS32R6 compact branch supportDaniel Sanders2016-03-1413-56/+358
| | | | | | | | | | | | | | | | | | | | | | | Summary: MIPSR6 introduces a class of branches called compact branches. Unlike the traditional MIPS branches which have a delay slot, compact branches do not have a delay slot. The instruction following the compact branch is only executed if the branch is not taken and must not be a branch. It works by generating compact branches for MIPS32R6 when the delay slot filler cannot fill a delay slot. Then, inspecting the generated code for forbidden slot hazards (a compact branch with an adjacent branch or other CTI) and inserting nops to clear this hazard. Patch by Simon Dardis. Reviewers: vkalintiris, dsanders Subscribers: MatzeB, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16353 llvm-svn: 263444
* [mips] Use range-based for loops. NFC.Vasileios Kalintiris2016-03-141-7/+5
| | | | llvm-svn: 263438
* [mips] Fix an issue with long double when function roundl is definedZlatko Buljan2016-03-141-2/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D17760 llvm-svn: 263428
* [mips] Range check uimm16_64Daniel Sanders2016-03-141-7/+8
| | | | | | | | | | | | Summary: Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D17725 llvm-svn: 263427
* [mips] Simplify ordering of range checked immediate classes.Daniel Sanders2016-03-141-29/+49
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: With the addition of checks to ensure that operands have a strict ordering it has become tricky to manage the order in the way I originally intended. This patch linearizes the ordering which simplifies the implementation but requires an order that is arbitrary in places. Here are some examples: * uimm4 < uimm5 < uimm6 * simm4 < uimm4 < simm5 < uimm5 * uimm5 < uimm5_plus1 (1..32) < uimm5_plus32 (32..63) < uimm6 The term 'superset' starts to break down here since the *_plus* classes are not true supersets of uimm5 (but they are still subsets of uimm6). * uimm5 < uimm5_64, and uimm5 < vsplat_uimm5 This is entirely arbitrary. We need an ordering and what we pick is unimportant since only one is possible for a given mnemonic. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D17723 llvm-svn: 263423
* [mips] Range check uimm6_lsl2.Daniel Sanders2016-03-144-43/+32
| | | | | | | | | | | | Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D17291 llvm-svn: 263419
* [mips] MIPSR6 Instruction itinerariesVasileios Kalintiris2016-03-113-65/+186
| | | | | | | | | | | | | | Summary: Defines instruction itineraries for common MIPSR6 instructions. Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: MatzeB, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D17198 llvm-svn: 263229
* [mips] Range check simm4.Daniel Sanders2016-03-114-34/+50
| | | | | | | | | | | | Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16811 llvm-svn: 263220
* [mips][microMIPS] Prevent usage of OR16_MMR6 instruction when code for ↵Zoran Jovanovic2016-03-042-2/+2
| | | | | | | | | | microMIPS is generated. Author: milena.vujosevic.janicic Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D17373 llvm-svn: 262725
* Revert "[mips] Promote the result of SETCC nodes to GPR width."Vasileios Kalintiris2016-03-0114-550/+418
| | | | | | | | | This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
* TableGen: Check scheduling models for completenessMatthias Braun2016-03-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | TableGen checks at compiletime that for scheduling models with "CompleteModel = 1" one of the following holds: - Is marked with the hasNoSchedulingInfo flag - The instruction is a subclass of Sched - There are InstRW definitions in the scheduling model Typical steps necessary to complete a model: - Ensure all pseudo instructions that are expanded before machine scheduling (usually everything handled with EmitYYY() functions in XXXTargetLowering). - If a CPU does not support some instructions mark the corresponding resource unsupported: "WriteRes<WriteXXX, []> { let Unsupported = 1; }". - Add missing scheduling information. Differential Revision: http://reviews.llvm.org/D17747 llvm-svn: 262384
* [mips] Promote the result of SETCC nodes to GPR width.Vasileios Kalintiris2016-03-0114-418/+550
| | | | | | | | | | | | | | | | | | | | Summary: This patch modifies the existing comparison, branch, conditional-move and select patterns, and adds new ones where needed. Also, the updated SLT{u,i,iu} set of instructions generate a GPR width result. The majority of the code changes in the Mips back-end fix the wrong assumption that the result of SETCC nodes always produce an i32 value. The changes in the common code path account for the fact that in 64-bit MIPS targets, i1 is promoted to i32 instead of i64. Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D10970 llvm-svn: 262316
* [mips] Range check uimm20 and fixed a bug this revealed.Daniel Sanders2016-02-298-76/+57
| | | | | | | | | | | | | | | | | | | Summary: The bug was that dextu's operand 3 would print 0-31 instead of 32-63 when printing assembly. This came up when replacing MipsInstPrinter::printUnsignedImm() with a version that could handle arbitrary bit widths. MipsAsmPrinter::printUnsignedImm*() don't seem to be used so they have been removed. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15521 llvm-svn: 262231
* [mips] Do not use SLL for ANY_EXTEND nodes as the high bits are undefined.Vasileios Kalintiris2016-02-291-1/+2
| | | | | | | | | | Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15420 llvm-svn: 262230
* [mips] Make isel select the correct DEXT variant up front.Daniel Sanders2016-02-295-34/+44
| | | | | | | | | | | | | | | | | Summary: Previously, it would always select DEXT and substitute any invalid matches for DEXTU/DEXTM during MipsMCCodeEmitter::encodeInstruction(). This works but causes problems when adding range checked immediates to IAS. Now isel selects the correct variant up front. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16810 llvm-svn: 262229
* [mips] Make symbols an acceptable branch target when expanding ↵Daniel Sanders2016-02-291-1/+2
| | | | | | | | | | | | compare-to-immediate-and-branch macros. Reviewers: vkalintiris Subscribers: llvm-commits, vkalintiris, dim, seanbruno, dsanders Differential Revision: http://reviews.llvm.org/D15369 llvm-svn: 262213
* [mips] Remove unused function declarations from MipsRegisterInfo.h. NFC.Vasileios Kalintiris2016-02-281-10/+0
| | | | llvm-svn: 262187
* [mips][microMIPS] Implement DINSU, DINSM, DINS instructionsHrvoje Varga2016-02-255-9/+61
| | | | | | Differential Revision: http://reviews.llvm.org/D16181 llvm-svn: 261860
* CodeGen: TII: Take MachineInstr& in predicate API, NFCDuncan P. N. Exon Smith2016-02-231-3/+3
| | | | | | | | | | | | | Change TargetInstrInfo API to take `MachineInstr&` instead of `MachineInstr*` in the functions related to predicated instructions (I'll try to come back later and get some of the rest). All of these functions require non-null parameters already, so references are more clear. As a bonus, this happens to factor away a host of implicit iterator => pointer conversions. No functionality change intended. llvm-svn: 261605
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