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* [SelectionDAG] Allow targets to specify legality of extloads' resultAhmed Bougacha2015-01-082-12/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | type (in addition to the memory type). The *LoadExt* legalization handling used to only have one type, the memory type. This forced users to assume that as long as the extload for the memory type was declared legal, and the result type was legal, the whole extload was legal. However, this isn't always the case. For instance, on X86, with AVX, this is legal: v4i32 load, zext from v4i8 but this isn't: v4i64 load, zext from v4i8 Whereas v4i64 is (arguably) legal, even without AVX2. Note that the same thing was done a while ago for truncstores (r46140), but I assume no one needed it yet for extloads, so here we go. Calls to getLoadExtAction were changed to add the value type, found manually in the surrounding code. Calls to setLoadExtAction were mechanically changed, by wrapping the call in a loop, to match previous behavior. The loop iterates over the MVT subrange corresponding to the memory type (FP vectors, etc...). I also pulled neighboring setTruncStoreActions into some of the loops; those shouldn't make a difference, as the additional types are illegal. (e.g., i128->i1 truncstores on PPC.) No functional change intended. Differential Revision: http://reviews.llvm.org/D6532 llvm-svn: 225421
* [CodeGen] Use MVT iterator_ranges in legality loops. NFC intended.Ahmed Bougacha2015-01-071-10/+6
| | | | | | | | A few loops do trickier things than just iterating on an MVT subset, so I'll leave them be for now. Follow-up of r225387. llvm-svn: 225392
* Remove dead variable.Eric Christopher2015-01-062-2/+1
| | | | llvm-svn: 225233
* Use the same call off of the TargetMachine rather than the subtarget.Eric Christopher2015-01-061-1/+1
| | | | llvm-svn: 225232
* Rewrite the Mips16HardFloat pass to avoid using the Subtarget.Eric Christopher2015-01-064-26/+18
| | | | llvm-svn: 225231
* Replace several 'assert(false' with 'llvm_unreachable' or fold a condition ↵Craig Topper2015-01-054-11/+6
| | | | | | into the assert. llvm-svn: 225160
* Minor cleanup to all the switches after MatchInstructionImpl in all the ↵Craig Topper2015-01-031-3/+2
| | | | | | | | AsmParsers. Make sure they all have llvm_unreachable on the default path out of the switch. Remove unnecessary "default: break". Remove a 'return' after unreachable. Fix some indentation. llvm-svn: 225114
* [mips][microMIPS] Relocate with symbol for micromips symbolsZoran Jovanovic2014-12-301-1/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D6796 llvm-svn: 225008
* [mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructionsJozef Kolek2014-12-235-7/+75
| | | | | | Differential Revision: http://reviews.llvm.org/D5204 llvm-svn: 224785
* [mips][microMIPS] Implement LWSP and SWSP instructionsJozef Kolek2014-12-236-0/+90
| | | | | | Differential Revision: http://reviews.llvm.org/D6416 llvm-svn: 224771
* Fix UBSan bootstrap: replace shift of negative value with multiplication.Alexey Samsonov2014-12-231-1/+1
| | | | llvm-svn: 224752
* Remove unused variable and initialization.Eric Christopher2014-12-201-4/+1
| | | | llvm-svn: 224655
* Remove unused variable, initializer, and accessor.Eric Christopher2014-12-192-10/+4
| | | | llvm-svn: 224650
* [mips][microMIPS] Fix bugs related to atomic SC/LL instructionsJozef Kolek2014-12-181-4/+8
| | | | | | | | | Fix bugs related to atomic microMIPS SC/LL instructions: While expanding atomic operations the mips32r2 encoding was emitted instead of microMIPS. Differential Revision: http://reviews.llvm.org/D6659 llvm-svn: 224524
* MipsABIInfo class is used in different libraries. Moving the files to ↵Vladimir Medic2014-12-175-2/+2
| | | | | | MCTargetDesc folder(LLVMMipsDesc library) prevents linkage errors. There are no functional changes. llvm-svn: 224427
* [mips] Set GCC-compatible MIPS asssembler options before inline asm blocks.Toma Tabacu2014-12-173-4/+24
| | | | | | | | | | | | | | | | | | | | Summary: When generating MIPS assembly, LLVM always overrides the default assembler options by emitting the '.set noreorder', '.set nomacro' and '.set noat' directives, while GCC uses the default options if an assembly-level function contains inline assembly code. This becomes a problem when the code generated by LLVM is interleaved with inline assembly which assumes GCC-like assembler options (from Linux, for example). This patch fixes these conflicts by setting the appropriate assembler options at the beginning of an inline asm block and popping them at the end. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6637 llvm-svn: 224425
* The single check for N64 inside MipsDisassemblerBase's subclasses is ↵Vladimir Medic2014-12-161-4/+4
| | | | | | actually wrong. It should be testing for FeatureGP64bit.There are no functional changes. llvm-svn: 224339
* [mips][microMIPS] Implement SWP and LWP instructionsZoran Jovanovic2014-12-167-1/+101
| | | | | | Differential Revision: http://reviews.llvm.org/D5667 llvm-svn: 224338
* Add disassembler tests for mips3 platform. There are no functional changes.Vladimir Medic2014-12-151-1/+2
| | | | llvm-svn: 224253
* [mips] Enable code generation for MIPS-III.Vasileios Kalintiris2014-12-123-9/+17
| | | | | | | | | | | | | | | | | | Summary: This commit enables the MIPS-III target and adds support for code generation of SELECT nodes. We have to use pseudo-instructions with custom inserters for these nodes as MIPS-III CPUs do not have conditional-move instructions. Depends on D6212 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6464 llvm-svn: 224128
* [mips] Support SELECT nodes for targets that don't have conditional-move ↵Vasileios Kalintiris2014-12-124-0/+129
| | | | | | | | | | | | | | | | | | | | | | | | instructions. Summary: For Mips targets that do not have conditional-move instructions, ie. targets before MIPS32 and MIPS-IV, we have to insert a diamond control-flow pattern in order to support SELECT nodes. In order to do that, we add pseudo-instructions with a custom inserter that emits the necessary control-flow that selects the correct value. With this patch we add complete support for code generation of Mips-II targets based on the LLVM test-suite. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6212 llvm-svn: 224124
* Enable MachineVerifier in debug mode for X86, ARM, AArch64, Mips.Matthias Braun2014-12-111-2/+2
| | | | llvm-svn: 224075
* [CodeGen] Add print and verify pass after each MachineFunctionPass by defaultMatthias Braun2014-12-111-12/+7
| | | | | | | | | | | | | | | | | | | Previously print+verify passes were added in a very unsystematic way, which is annoying when debugging as you miss intermediate steps and allows bugs to stay unnotice when no verification is performed. To make this change practical I added the possibility to explicitely disable verification. I used this option on all places where no verification was performed previously (because alot of places actually don't pass the MachineVerifier). In the long term these problems should be fixed properly and verification enabled after each pass. I'll enable some more verification in subsequent commits. This is the 2nd attempt at this after realizing that PassManager::add() may actually delete the pass. llvm-svn: 224059
* This reverts commit r224043 and r224042.Rafael Espindola2014-12-111-5/+10
| | | | | | check-llvm was failing. llvm-svn: 224045
* Enable machineverifier in debug mode for X86, ARM, AArch64, MipsMatthias Braun2014-12-111-2/+2
| | | | llvm-svn: 224043
* [CodeGen] Add print and verify pass after each MachineFunctionPass by defaultMatthias Braun2014-12-111-12/+7
| | | | | | | | | | | | | | | | Previously print+verify passes were added in a very unsystematic way, which is annoying when debugging as you miss intermediate steps and allows bugs to stay unnotice when no verification is performed. To make this change practical I added the possibility to explicitely disable verification. I used this option on all places where no verification was performed previously (because alot of places actually don't pass the MachineVerifier). In the long term these problems should be fixed properly and verification enabled after each pass. I'll enable some more verification in subsequent commits. llvm-svn: 224042
* [mips][microMIPS] Implement CodeGen support for LI16 instruction.Jozef Kolek2014-12-112-4/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D5840 llvm-svn: 224017
* test commit (spelling correction)Mohit K. Bhakkad2014-12-091-1/+1
| | | | llvm-svn: 223758
* [mips] Add Mips-specific CCIf's for accessing the MipsCCState. NFC.Daniel Sanders2014-12-081-13/+28
| | | | | | | | | | | | Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6213 llvm-svn: 223662
* Allow target to specify prefix for labelsMatt Arsenault2014-12-041-0/+1
| | | | | | | | Use the MCAsmInfo instead of the DataLayout, and allow specifying a custom prefix for labels specifically. HSAIL requires that labels begin with @, but global symbols with &. llvm-svn: 223323
* [mips] Fix passing of small structures for big-endian O32.Daniel Sanders2014-12-021-0/+16
| | | | | | | | | | | | | | | | | | | Summary: Like N32/N64, they must be passed in the upper bits of the register. The new code could be merged with the existing if-statements but I've refrained from doing this since it will make porting the O32 implementation to tablegen harder later. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6463 llvm-svn: 223148
* The andi16, addiusp and jraddiusp micromips instructions were missing ↵Vladimir Medic2014-12-012-0/+42
| | | | | | dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests. llvm-svn: 223006
* [mips][microMIPS] Implement NOP aliasesJozef Kolek2014-11-292-1/+4
| | | | | | | | | This patch implements microMIPS 16-bit (MOVE16 $0, $0) and 32-bit (SLL $0, $0, 0) NOP aliases. http://reviews.llvm.org/D6440 llvm-svn: 222953
* [mips][microMIPS] Implement SWM16 and LWM16 instructionsZoran Jovanovic2014-11-277-0/+147
| | | | | | Differential Revision: http://reviews.llvm.org/D5579 llvm-svn: 222901
* [mips][microMIPS] Implement BREAK16 and SDBBP16 instructionsJozef Kolek2014-11-272-0/+17
| | | | | | | | Patch by Radovan Obradovic. Differential Revision: http://reviews.llvm.org/D5048 llvm-svn: 222900
* [mips] Add synci instruction.Daniel Sanders2014-11-273-1/+56
| | | | | | | | | | | | | | Patch by Amaury Pouly Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6421 llvm-svn: 222899
* [mips][microMIPS] Implement disassembler support for 16-bit instructions ↵Jozef Kolek2014-11-272-3/+69
| | | | | | | | LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5 Differential Revision: http://reviews.llvm.org/D6419 llvm-svn: 222887
* [mips][microMIPS] Implement disassembler support for 16-bit instructions ↵Jozef Kolek2014-11-263-4/+67
| | | | | | | | LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
* Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.Craig Topper2014-11-262-14/+14
| | | | llvm-svn: 222801
* [mips][micromips] Use call instructions with short delay slotsZoran Jovanovic2014-11-251-21/+49
| | | | | | Differential Revision: http://reviews.llvm.org/D6338 llvm-svn: 222752
* [mips][microMIPS] Fix JRADDIUSP instructionJozef Kolek2014-11-241-1/+0
| | | | | | | | | Fix JRADDIUSP instruction, remove delay slot flag because this instruction doesn't have delay slot. Differential Revision: http://reviews.llvm.org/D6365 llvm-svn: 222658
* [mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructionsJozef Kolek2014-11-245-0/+164
| | | | | | Differential Revision: http://reviews.llvm.org/D5122 llvm-svn: 222653
* [mips][microMIPS] Implement 16-bit instructions registers including ZERO ↵Jozef Kolek2014-11-243-0/+41
| | | | | | | | | | instead of S0 Implement microMIPS 16-bit instructions register set: $0, $2-$7 and $17. Differential Revision: http://reviews.llvm.org/D5780 llvm-svn: 222652
* [mips][microMIPS] Implement disassembler support for 16-bit instructionsJozef Kolek2014-11-242-14/+57
| | | | | | | | | | | With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
* [mips][microMIPS] This patch implements functionality in MIPS delay slotJozef Kolek2014-11-213-11/+53
| | | | | | | | | | | filler such as if delay slot filler have to put NOP instruction into the delay slot of microMIPS BEQ or BNE instruction which uses the register $0, then instead of emitting NOP this instruction is replaced by the corresponding microMIPS compact branch instruction, i.e. BEQZC or BNEZC. Differential Revision: http://reviews.llvm.org/D3566 llvm-svn: 222580
* Remove a bunch of unnecessary typecasts to 'const TargetRegisterClass *'Craig Topper2014-11-213-15/+7
| | | | llvm-svn: 222509
* Fix more instances of -Wsentinel on Windows with s/NULL/nullptr/Reid Kleckner2014-11-201-1/+1
| | | | | | Follow up to r221940, where I must not have caught em all. NFC llvm-svn: 222481
* Add out of line virtual destructors to all LLVMTargetMachine subclassesReid Kleckner2014-11-202-0/+3
| | | | | | | | | | | | | | | | | These recently all grew a unique_ptr<TargetLoweringObjectFile> member in r221878. When anyone calls a virtual method of a class, clang-cl requires all virtual methods to be semantically valid. This includes the implicit virtual destructor, which triggers instantiation of the unique_ptr destructor, which fails because the type being deleted is incomplete. This is just part of the ongoing saga of PR20337, which is affecting Blink as well. Because the MSVC ABI doesn't have key functions, we end up referencing the vtable and implicit destructor on any virtual call through a class. We don't actually end up emitting the dtor, so it'd be good if we could avoid this unneeded type completion work. llvm-svn: 222480
* [mips][micromips] Implement SWM32 and LWM32 instructionsZoran Jovanovic2014-11-1910-6/+288
| | | | | | Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
* [mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions.Jozef Kolek2014-11-191-4/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D6169 llvm-svn: 222355
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