| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
type (in addition to the memory type).
The *LoadExt* legalization handling used to only have one type, the
memory type. This forced users to assume that as long as the extload
for the memory type was declared legal, and the result type was legal,
the whole extload was legal.
However, this isn't always the case. For instance, on X86, with AVX,
this is legal:
v4i32 load, zext from v4i8
but this isn't:
v4i64 load, zext from v4i8
Whereas v4i64 is (arguably) legal, even without AVX2.
Note that the same thing was done a while ago for truncstores (r46140),
but I assume no one needed it yet for extloads, so here we go.
Calls to getLoadExtAction were changed to add the value type, found
manually in the surrounding code.
Calls to setLoadExtAction were mechanically changed, by wrapping the
call in a loop, to match previous behavior. The loop iterates over
the MVT subrange corresponding to the memory type (FP vectors, etc...).
I also pulled neighboring setTruncStoreActions into some of the loops;
those shouldn't make a difference, as the additional types are illegal.
(e.g., i128->i1 truncstores on PPC.)
No functional change intended.
Differential Revision: http://reviews.llvm.org/D6532
llvm-svn: 225421
|
|
|
|
|
|
|
|
| |
A few loops do trickier things than just iterating on an MVT subset,
so I'll leave them be for now.
Follow-up of r225387.
llvm-svn: 225392
|
|
|
|
| |
llvm-svn: 225233
|
|
|
|
| |
llvm-svn: 225232
|
|
|
|
| |
llvm-svn: 225231
|
|
|
|
|
|
| |
into the assert.
llvm-svn: 225160
|
|
|
|
|
|
|
|
| |
AsmParsers.
Make sure they all have llvm_unreachable on the default path out of the switch. Remove unnecessary "default: break". Remove a 'return' after unreachable. Fix some indentation.
llvm-svn: 225114
|
|
|
|
|
|
| |
Differential Revision: http://reviews.llvm.org/D6796
llvm-svn: 225008
|
|
|
|
|
|
| |
Differential Revision: http://reviews.llvm.org/D5204
llvm-svn: 224785
|
|
|
|
|
|
| |
Differential Revision: http://reviews.llvm.org/D6416
llvm-svn: 224771
|
|
|
|
| |
llvm-svn: 224752
|
|
|
|
| |
llvm-svn: 224655
|
|
|
|
| |
llvm-svn: 224650
|
|
|
|
|
|
|
|
|
| |
Fix bugs related to atomic microMIPS SC/LL instructions: While expanding atomic
operations the mips32r2 encoding was emitted instead of microMIPS.
Differential Revision: http://reviews.llvm.org/D6659
llvm-svn: 224524
|
|
|
|
|
|
| |
MCTargetDesc folder(LLVMMipsDesc library) prevents linkage errors. There are no functional changes.
llvm-svn: 224427
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Summary:
When generating MIPS assembly, LLVM always overrides the default assembler options by emitting the '.set noreorder', '.set nomacro' and '.set noat' directives,
while GCC uses the default options if an assembly-level function contains inline assembly code.
This becomes a problem when the code generated by LLVM is interleaved with inline assembly which assumes GCC-like assembler options (from Linux, for example).
This patch fixes these conflicts by setting the appropriate assembler options at the beginning of an inline asm block and popping them at the end.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D6637
llvm-svn: 224425
|
|
|
|
|
|
| |
actually wrong. It should be testing for FeatureGP64bit.There are no functional changes.
llvm-svn: 224339
|
|
|
|
|
|
| |
Differential Revision: http://reviews.llvm.org/D5667
llvm-svn: 224338
|
|
|
|
| |
llvm-svn: 224253
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Summary:
This commit enables the MIPS-III target and adds support for code
generation of SELECT nodes. We have to use pseudo-instructions with
custom inserters for these nodes as MIPS-III CPUs do not have
conditional-move instructions.
Depends on D6212
Reviewers: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D6464
llvm-svn: 224128
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
instructions.
Summary:
For Mips targets that do not have conditional-move instructions, ie. targets
before MIPS32 and MIPS-IV, we have to insert a diamond control-flow
pattern in order to support SELECT nodes. In order to do that, we add
pseudo-instructions with a custom inserter that emits the necessary
control-flow that selects the correct value.
With this patch we add complete support for code generation of Mips-II targets
based on the LLVM test-suite.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D6212
llvm-svn: 224124
|
|
|
|
| |
llvm-svn: 224075
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Previously print+verify passes were added in a very unsystematic way, which is
annoying when debugging as you miss intermediate steps and allows bugs to stay
unnotice when no verification is performed.
To make this change practical I added the possibility to explicitely disable
verification. I used this option on all places where no verification was
performed previously (because alot of places actually don't pass the
MachineVerifier).
In the long term these problems should be fixed properly and verification
enabled after each pass. I'll enable some more verification in subsequent
commits.
This is the 2nd attempt at this after realizing that PassManager::add() may
actually delete the pass.
llvm-svn: 224059
|
|
|
|
|
|
| |
check-llvm was failing.
llvm-svn: 224045
|
|
|
|
| |
llvm-svn: 224043
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Previously print+verify passes were added in a very unsystematic way, which is
annoying when debugging as you miss intermediate steps and allows bugs to stay
unnotice when no verification is performed.
To make this change practical I added the possibility to explicitely disable
verification. I used this option on all places where no verification was
performed previously (because alot of places actually don't pass the
MachineVerifier).
In the long term these problems should be fixed properly and verification
enabled after each pass. I'll enable some more verification in subsequent
commits.
llvm-svn: 224042
|
|
|
|
|
|
| |
Differential Revision: http://reviews.llvm.org/D5840
llvm-svn: 224017
|
|
|
|
| |
llvm-svn: 223758
|
|
|
|
|
|
|
|
|
|
|
|
| |
Reviewers: vmedic
Reviewed By: vmedic
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D6213
llvm-svn: 223662
|
|
|
|
|
|
|
|
| |
Use the MCAsmInfo instead of the DataLayout, and allow
specifying a custom prefix for labels specifically. HSAIL
requires that labels begin with @, but global symbols with &.
llvm-svn: 223323
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Summary:
Like N32/N64, they must be passed in the upper bits of the register.
The new code could be merged with the existing if-statements but I've
refrained from doing this since it will make porting the O32 implementation
to tablegen harder later.
Reviewers: vmedic
Reviewed By: vmedic
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D6463
llvm-svn: 223148
|
|
|
|
|
|
| |
dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.
llvm-svn: 223006
|
|
|
|
|
|
|
|
|
| |
This patch implements microMIPS 16-bit (MOVE16 $0, $0) and
32-bit (SLL $0, $0, 0) NOP aliases.
http://reviews.llvm.org/D6440
llvm-svn: 222953
|
|
|
|
|
|
| |
Differential Revision: http://reviews.llvm.org/D5579
llvm-svn: 222901
|
|
|
|
|
|
|
|
| |
Patch by Radovan Obradovic.
Differential Revision: http://reviews.llvm.org/D5048
llvm-svn: 222900
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Patch by Amaury Pouly
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D6421
llvm-svn: 222899
|
|
|
|
|
|
|
|
| |
LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5
Differential Revision: http://reviews.llvm.org/D6419
llvm-svn: 222887
|
|
|
|
|
|
|
|
| |
LBU16, LHU16, LW16, SB16, SH16 and SW16
Differential Revision: http://reviews.llvm.org/D6405
llvm-svn: 222847
|
|
|
|
| |
llvm-svn: 222801
|
|
|
|
|
|
| |
Differential Revision: http://reviews.llvm.org/D6338
llvm-svn: 222752
|
|
|
|
|
|
|
|
|
| |
Fix JRADDIUSP instruction, remove delay slot flag because this instruction
doesn't have delay slot.
Differential Revision: http://reviews.llvm.org/D6365
llvm-svn: 222658
|
|
|
|
|
|
| |
Differential Revision: http://reviews.llvm.org/D5122
llvm-svn: 222653
|
|
|
|
|
|
|
|
|
|
| |
instead of S0
Implement microMIPS 16-bit instructions register set: $0, $2-$7 and $17.
Differential Revision: http://reviews.llvm.org/D5780
llvm-svn: 222652
|
|
|
|
|
|
|
|
|
|
|
| |
With the help of new method readInstruction16() two bytes are read and
decodeInstruction() is called with DecoderTableMicroMips16, if this fails
four bytes are read and decodeInstruction() is called with
DecoderTableMicroMips32.
Differential Revision: http://reviews.llvm.org/D6149
llvm-svn: 222648
|
|
|
|
|
|
|
|
|
|
|
| |
filler such as if delay slot filler have to put NOP instruction into the
delay slot of microMIPS BEQ or BNE instruction which uses the register $0,
then instead of emitting NOP this instruction is replaced by the corresponding
microMIPS compact branch instruction, i.e. BEQZC or BNEZC.
Differential Revision: http://reviews.llvm.org/D3566
llvm-svn: 222580
|
|
|
|
| |
llvm-svn: 222509
|
|
|
|
|
|
| |
Follow up to r221940, where I must not have caught em all. NFC
llvm-svn: 222481
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
These recently all grew a unique_ptr<TargetLoweringObjectFile> member in
r221878. When anyone calls a virtual method of a class, clang-cl
requires all virtual methods to be semantically valid. This includes the
implicit virtual destructor, which triggers instantiation of the
unique_ptr destructor, which fails because the type being deleted is
incomplete.
This is just part of the ongoing saga of PR20337, which is affecting
Blink as well. Because the MSVC ABI doesn't have key functions, we end
up referencing the vtable and implicit destructor on any virtual call
through a class. We don't actually end up emitting the dtor, so it'd be
good if we could avoid this unneeded type completion work.
llvm-svn: 222480
|
|
|
|
|
|
| |
Differential Revision: http://reviews.llvm.org/D5519
llvm-svn: 222367
|
|
|
|
|
|
| |
Differential Revision: http://reviews.llvm.org/D6169
llvm-svn: 222355
|