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* [mips][microMIPS] Implement CodeGen support for 16-bit instruction ADDIUR2.Jozef Kolek2014-11-191-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D5800 llvm-svn: 222352
* [mips][microMIPS] Implement CodeGen support for ADDIUS5 instruction.Jozef Kolek2014-11-192-3/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D5799 llvm-svn: 222351
* [mips][microMIPS] Implement LWXS instruction.Jozef Kolek2014-11-192-0/+23
| | | | | | Differential Revision: http://reviews.llvm.org/D5407 llvm-svn: 222348
* [mips][microMIPS] Implement SDBBP and RDHWR instructions.Jozef Kolek2014-11-194-4/+31
| | | | | | Differential Revision: http://reviews.llvm.org/D5240 llvm-svn: 222347
* Update SetVector to rely on the underlying set's insert to return a ↵David Blaikie2014-11-191-1/+2
| | | | | | | | | | | | | pair<iterator, bool> This is to be consistent with StringSet and ultimately with the standard library's associative container insert function. This lead to updating SmallSet::insert to return pair<iterator, bool>, and then to update SmallPtrSet::insert to return pair<iterator, bool>, and then to update all the existing users of those functions... llvm-svn: 222334
* Test commit to verify that commit access works.Jozef Kolek2014-11-181-1/+1
| | | | llvm-svn: 222244
* Fix build of Mips code with MSVC by using our macro instead of ↵Reid Kleckner2014-11-142-5/+4
| | | | | | __attribute__((unused)) directly llvm-svn: 221956
* First stage of call lowering for Mips fast-iselReed Kotler2014-11-133-2/+319
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This has most of what is needed for mips fast-isel call lowering for O32. What is missing I will add on the next patch because this patch is already too large. It should not be doing anything wrong but it will punt on some cases that it is basically capable of doing. The mechanism is there for parameters to be passed on the stack but I have not enabled it because it serves as a way for now to prevent some of the strange cases of O32 register passing that I have not fully checked yet and have some issues. The Mips O32 abi rules are very complicated as far how data is passed in floating and integer registers. However there is a way to think about this all very simply and this implementation reflects that. Basically, the ABI rules are written as if everything is passed on the stack and aligned as such. Once that is conceptually done, it is nearly trivial to reassign those locations to registers and then all the complexity disappears. So I have told tablegen that all the data is passed on the stack and during the lowering I fix this by assigning to registers as per the ABI doc. This has been my approach and you can line up what I did with the ABI document and see 1 to 1 what is going on. Test Plan: callabi.ll Reviewers: dsanders Reviewed By: dsanders Subscribers: jholewinski, echristo, ahatanak, llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D5714 llvm-svn: 221948
* We can get the TLOF from the TargetMachine - so constructor no longer ↵Aditya Nandakumar2014-11-131-1/+1
| | | | | | requires TargetLoweringObjectFile to be passed. llvm-svn: 221926
* This patch changes the ownership of TLOF from TargetLoweringBase to ↵Aditya Nandakumar2014-11-133-4/+10
| | | | | | TargetMachine so that different subtargets could share the TLOF effectively llvm-svn: 221878
* [mips][micromips] Add predicate 'InMicroMips' at CodeGen patterns for ↵Zoran Jovanovic2014-11-121-1/+2
| | | | | | | | microMIPS instructions Differential Revision: http://reviews.llvm.org/D6198 llvm-svn: 221780
* Pass an ArrayRef to MCDisassembler::getInstruction.Rafael Espindola2014-11-121-15/+11
| | | | | | | | | | | | With this patch MCDisassembler::getInstruction takes an ArrayRef<uint8_t> instead of a MemoryObject. Even on X86 there is a maximum size an instruction can have. Given that, it seems way simpler and more efficient to just pass an ArrayRef to the disassembler instead of a MemoryObject and have it do a virtual call every time it wants some extra bytes. llvm-svn: 221751
* [mips] Add preliminary support for the MIPS II target.Vasileios Kalintiris2014-11-113-5/+13
| | | | | | | | | | | | | | | | | | | Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
* [mips] Add hardware register name "hwr_ulr" ($29)Vasileios Kalintiris2014-11-111-0/+1
| | | | | | | | | | The canonical name when printing assembly is still $29. The reason is that GAS does not accept "$hwr_ulr" at the moment. This addresses the comments from r221307, which reverted the original commit r221299. llvm-svn: 221685
* Recommit "[mips] Add names and tests for the hardware registers"Vasileios Kalintiris2014-11-112-2/+37
| | | | | | | The original commit r221299 was reverted in r221307. I removed the name "hrw_ulr" ($29) from the original commit because two tests were failing. llvm-svn: 221681
* MCAsmParserExtension has a copy of the MCAsmParser. Use it.Rafael Espindola2014-11-111-8/+49
| | | | | | Base classes were storing a second copy. llvm-svn: 221667
* Misc style fixes. NFC.Rafael Espindola2014-11-101-78/+53
| | | | | | | | | | | | | This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
* [mips][microMIPS] Fix issue with delay slot filler and microMIPSZoran Jovanovic2014-11-101-11/+19
| | | | | | Differential Revision: http://reviews.llvm.org/D6193 llvm-svn: 221612
* [mips] Fix sret arguments for N32/N64 which were accidentally broken in r221534.Daniel Sanders2014-11-101-0/+1
| | | | llvm-svn: 221604
* [mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit ↵Daniel Sanders2014-11-075-43/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | structs... Summary: ... and after all that refactoring, it's possible to distinguish softfloat floating point values from integers so this patch no longer breaks softfloat to do it. Remove direct handling of i32's in the N32/N64 ABI by promoting them to i64. This more closely reflects the ABI documentation and also fixes problems with stack arguments on big-endian targets. We now rely on signext/zeroext annotations (already generated by clang) and the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero extends. It was not possible to convert three tests to use signext/zeroext. These tests are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a vector type so we just accept the sign extends here for now. These tests don't pass the vectors the same way clang does (clang puts multiple elements in the same argument, these map 1 element to 1 argument) so we don't need to worry too much about it. With this patch, all known N32/N64 bugs should be fixed and we now pass the first 10,000 tests generated by ABITest.py. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6117 llvm-svn: 221534
* [mips] Removed the remainder of MipsCC. NFC.Daniel Sanders2014-11-072-39/+24
| | | | | | | | | | | | | | | | | Summary: One of the calls to AllocateStack (the one in LowerCall) doesn't look like it should be there but it was there before and removing it breaks the frame size calculation. Reviewers: vmedic, theraven Reviewed By: theraven Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6116 llvm-svn: 221529
* [mips] Remove MipsCC::reservedArgArea() in favour of ↵Daniel Sanders2014-11-074-18/+29
| | | | | | | | | | | | | | | | MipsABIInfo::GetCalleeAllocdArgSizeInBytes(). NFC. Summary: Reviewers: theraven, vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6115 llvm-svn: 221528
* MipsCCState.h: Use LLVM_DELETED_FUNCTION for msc17.NAKAMURA Takumi2014-11-071-2/+2
| | | | llvm-svn: 221527
* [mips] Move MipsCCState to a separate file and clang-formatted it.Daniel Sanders2014-11-074-199/+260
| | | | | | | | | | | | | | Summary: Depends on D6113 Reviewers: theraven, vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6114 llvm-svn: 221525
* [mips] Fix unused variable warnings introduced in r221521Daniel Sanders2014-11-071-9/+0
| | | | llvm-svn: 221522
* [mips] Remove remaining use of MipsCC::intArgRegs() in favour of ↵Daniel Sanders2014-11-074-15/+18
| | | | | | | | | | | | | | | | MipsABIInfo::GetByValArgRegs() and MipsABIInfo::GetVarArgRegs() Summary: Depends on D6112 Reviewers: theraven, vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6113 llvm-svn: 221521
* [mips] Remove MipsCC::getRegVT(). NFCDaniel Sanders2014-11-072-22/+0
| | | | | | | | | | | | | | Summary: It's no longer used. Reviewers: vmedic, theraven Reviewed By: theraven Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6112 llvm-svn: 221519
* [mips] Remove MipsCC::analyzeCallOperands in favour of ↵Daniel Sanders2014-11-073-48/+39
| | | | | | | | | | | | | | | | | | CCState::AnalyzeCallOperands. NFC Summary: In addition to the usual f128 workaround, it was also necessary to provide a means of accessing ArgListEntry::IsFixed. Reviewers: theraven, vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6111 llvm-svn: 221518
* [mips] Move SpecialCallingConv to MipsCCState and use it from ↵Daniel Sanders2014-11-073-46/+48
| | | | | | | | | | | | | | | | tablegen-erated code. NFC Summary: In the long run, it should probably become a calling convention in its own right but for now just move it out of MipsISelLowering::analyzeCallOperands() so that we can drop this function in favour of CCState::AnalyzeCallOperands(). Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6085 llvm-svn: 221517
* [mips] Removed IsVarArg from MipsISelLowering::analyzeCallOperands(). NFC.Daniel Sanders2014-11-072-8/+6
| | | | | | | | | | | Summary: CCState objects already carry this information in their isVarArg() method. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6084 llvm-svn: 221516
* [mips] Removed IsSoftFloat from MipsISelLowering::analyzeCallOperands(). NFCDaniel Sanders2014-11-062-6/+5
| | | | | | | | | | | | | | | | | Summary: It isn't used anymore. Depends on D6081 Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6083 llvm-svn: 221463
* [mips] Removed MipsISelLowering::analyzeFormalArguments() in favour of ↵Daniel Sanders2014-11-062-33/+8
| | | | | | | | | | | | | | | | | | | CCState::AnalyzeFormalArguments() Summary: As with returns, we must be able to identify f128 arguments despite them being lowered away. We do this with a pre-analyze step that builds a vector and then we use this vector from the tablegen-erated code. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6081 llvm-svn: 221461
* [mips] Tolerate the use of the %z inline asm operand modifier with ↵Toma Tabacu2014-11-061-7/+5
| | | | | | | | | | | | | | | | | | | | | | non-immediates. Summary: Currently, we give an error if %z is used with non-immediates, instead of continuing as if the %z isn't there. For example, you use the %z operand modifier along with the "Jr" constraints ("r" makes the operand a register, and "J" makes it an immediate, but only if its value is 0). In this case, you want the compiler to print "$0" if the inline asm input operand turns out to be an immediate zero and you want it to print the register containing the operand, if it's not. We give an error in the latter case, and we shouldn't (GCC also doesn't). Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6023 llvm-svn: 221453
* [mips] Add the following MIPS options that control gp-relative addressing ofSasa Stankovic2014-11-065-42/+111
| | | | | | | | | small data items: -mgpopt, -mlocal-sdata, -mextern-sdata. Implement gp-relative addressing for constants. Differential Revision: http://reviews.llvm.org/D4903 llvm-svn: 221450
* [mips] Improve error/warning messages and testing for the .cpload assembler ↵Toma Tabacu2014-11-061-2/+11
| | | | | | | | | | | | | | | | | | directive. Summary: Improved warning message when using .cpload inside a reorder section and added an error message for using .cpload with Mips16 enabled. Modified the tests to fit with the changes mentioned above, added a test-case for the N32 ABI in cpload.s and did some reformatting to make the tests easier to read. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5465 llvm-svn: 221447
* ps][microMIPS] Implement CodeGen support for ANDI16 instructionZoran Jovanovic2014-11-052-2/+13
| | | | llvm-svn: 221371
* ps][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructionsZoran Jovanovic2014-11-052-9/+22
| | | | llvm-svn: 221369
* [mips][microMIPS] Implement ANDI16 instructionZoran Jovanovic2014-11-055-0/+64
| | | | llvm-svn: 221367
* [mips][microMIPS] Mark symbols as microMIPS if necessaryZoran Jovanovic2014-11-052-0/+52
| | | | | | Differential Revision: http://reviews.llvm.org/D6039 llvm-svn: 221355
* Reverted revisions 221351, 221352 and 221353.Zoran Jovanovic2014-11-056-99/+11
| | | | llvm-svn: 221354
* [mips][microMIPS] Implement CodeGen support for ANDI16 instructionZoran Jovanovic2014-11-052-2/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D5797 llvm-svn: 221353
* [mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructionsZoran Jovanovic2014-11-052-9/+22
| | | | | | Differential Revision: http://reviews.llvm.org/D5933 llvm-svn: 221352
* [mips][microMIPS] Implement ANDI16 instructionZoran Jovanovic2014-11-055-0/+64
| | | | | | Differential Revision: http://reviews.llvm.org/D5163 llvm-svn: 221351
* Revert "[mips] Add names and tests for the hardware registers"Rafael Espindola2014-11-042-39/+2
| | | | | | | | | | | | | This reverts commit r221299. The tests LLVM :: MC/Disassembler/Mips/mips32.txt LLVM :: MC/Disassembler/Mips/mips32_le.txt were failing. llvm-svn: 221307
* [mips] Move COP2 & COP3 load/store instructions from MipsInstrFPU.td to ↵Vasileios Kalintiris2014-11-042-56/+54
| | | | | | | | | | | | | | MipsInstrInfo.td. NFC. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5843 llvm-svn: 221300
* [mips] Add names and tests for the hardware registersVasileios Kalintiris2014-11-042-2/+39
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5763 llvm-svn: 221299
* [mips] Improve support for the .set mips16/nomips16 assembler directives.Toma Tabacu2014-11-041-6/+22
| | | | | | | | | | | | | | | | | | | Summary: Appropriately set/clear the FeatureBit for Mips16 when these assembler directives are used and also emit ".set nomips16" (previously, only ".set mips16" was being emitted). These improvements allow for better testing of the .cpload/.cprestore assembler directives (which are not supposed to work when Mips16 is enabled). Test Plan: The test is bare-bones because there are no MC tests for Mips16 instructions (there's only one, which checks that the Mips16 ELF header flag gets set), and that suggests to me that it has not been implemented yet in the IAS. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5462 llvm-svn: 221277
* [mips] Remove unused prototype and variable. NFC.Daniel Sanders2014-11-032-5/+0
| | | | llvm-svn: 221146
* Re-commit r221056 and others with fix, "[mips] Move F128 argument handling ↵Daniel Sanders2014-11-0210-175/+255
| | | | | | | | | into MipsCCState as we did for returns. NFC." sret arguments can never originate from an f128 argument so we detect sret arguments and push false into OriginalArgWasF128. llvm-svn: 221102
* Revert r221056 and others, "[mips] Move F128 argument handling into ↵NAKAMURA Takumi2014-11-0210-246/+175
| | | | | | | | | | | | | MipsCCState as we did for returns. NFC." r221056 "[mips] Move F128 argument handling into MipsCCState as we did for returns. NFC." r221058 "[mips] Fix unused variable warning introduced in r221056" r221059 "[mips] Move all ByVal handling into CCState and tablegen-erated code. NFC." r221061 "Renamed CCState members that appear to misspell 'Processed' as 'Proceed'. NFC." It cuased an undefined behavior in LLVM :: CodeGen/Mips/return-vector.ll. llvm-svn: 221081
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