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* [mips] For indirect calls we don't need $gp to point to .got. Mips linkerSasa Stankovic2014-10-016-15/+32
| | | | | | | | | doesn't generate lazy binding stub for a function whose address is taken in the program. Differential Revision: http://reviews.llvm.org/D5067 llvm-svn: 218744
* Add numeric extend, trunctate to mips fast-iselReed Kotler2014-09-301-5/+168
| | | | | | | | | | | | | | | | | | | | | Summary: Add numeric extend, trunctate to mips fast-isel Reactivates D4827 Test Plan: fpext.ll loadstoreconv.ll Reviewers: dsanders Subscribers: mcrosier Differential Revision: http://reviews.llvm.org/D5251 llvm-svn: 218681
* Simplify conditional.Eric Christopher2014-09-291-1/+1
| | | | llvm-svn: 218643
* Add soft-float to the key for the subtarget lookup in the TargetMachineEric Christopher2014-09-291-1/+13
| | | | | | | | | | | map, this makes sure that we can compile the same code for two different ABIs (hard and soft float) in the same module. Update one testcase accordingly (and fix some confusing naming) and add a new testcase as well with the ordering swapped which would highlight the problem. llvm-svn: 218632
* Fix spelling and reflow comments.Eric Christopher2014-09-291-6/+5
| | | | llvm-svn: 218631
* Fix unused variable warning added in r218509Daniel Sanders2014-09-261-1/+0
| | | | llvm-svn: 218510
* [mips] Generalize the handling of f128 return values to support f128 arguments.Daniel Sanders2014-09-263-50/+112
| | | | | | | | | | | | | | | | | | Summary: This will allow us to handle f128 arguments without duplicating code from CCState::AnalyzeFormalArguments() or CCState::AnalyzeCallOperands(). No functional change. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5292 llvm-svn: 218509
* Fix build breakage on MSVC 2013David Majnemer2014-09-261-1/+1
| | | | llvm-svn: 218499
* Target: Fix build breakage.David Majnemer2014-09-261-2/+2
| | | | | | No functional change intended. llvm-svn: 218497
* Add the first backend support for on demand subtarget creationEric Christopher2014-09-262-13/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | based on the Function. This is currently used to implement mips16 support in the mips backend via the existing module pass resetting the subtarget. Things to note: a) This involved running resetTargetOptions before creating a new subtarget so that code generation options like soft-float could be recognized when creating the new subtarget. This is to deal with initialization code in isel lowering that only paid attention to the initial value. b) Many of the existing testcases weren't using the soft-float feature correctly. I've corrected these based on the check values assuming that was the desired behavior. c) The mips port now pays attention to the target-cpu and target-features strings when generating code for a particular function. I've removed these from one function where the requested cpu and features didn't match the check lines in the testcase. llvm-svn: 218492
* [mips] Add CCValAssign::[ASZ]ExtUpper and CCPromoteToUpperBitsInType and ↵Daniel Sanders2014-09-252-4/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | handle struct's correctly on big-endian N32/N64 return values. Summary: The N32/N64 ABI's require that structs passed in registers are laid out such that spilling the register with 'sd' places the struct at the lowest address. For little endian this is trivial but for big-endian it requires that structs are shifted into the upper bits of the register. We also require that structs passed in registers have the 'inreg' attribute for big-endian N32/N64 to work correctly. This is because the tablegen-erated calling convention implementation only has access to the lowered form of struct arguments (one or more integers of up to 64-bits each) and is unable to determine the original type. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5286 llvm-svn: 218451
* [MCJIT] Nuke MachineRelocation and MachineCodeEmitter. Now that the old JIT isLang Hames2014-09-231-41/+0
| | | | | | gone they're no longer needed. llvm-svn: 218320
* constify the TargetMachine being passed through the Mips subtargetEric Christopher2014-09-198-15/+18
| | | | | | creation. llvm-svn: 218169
* Reverting NFC changes from r218050. Instead, the warning was disabled for ↵Aaron Ballman2014-09-181-1/+0
| | | | | | GCC in r218059, so these changes are no longer required. llvm-svn: 218062
* Fixing a bunch of -Woverloaded-virtual warnings due to hiding ↵Aaron Ballman2014-09-181-0/+1
| | | | | | getSubtargetImpl from the base class. NFC. llvm-svn: 218050
* [mips] Remove custom versions of CCState::AnalyzeReturn() and ↵Daniel Sanders2014-09-183-54/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CCState::AnalyzeCallReturn(). Summary: The N32/N64 ABI's return f128 values in $f0 and $f2 for hard-float and $v0 and $a0 for soft-float. The registers used in the soft-float case differ from the usual $v0, and $v1 specified for return values. Both cases were previously handled by duplicating the CCState::AnalyzeReturn() and CCState::AnalyzeCallReturn() functions and modifying them to delegate to a different assignment function for f128 and further replace the register type for the hard-float case. There is a simpler way to do both of these. We now use the common functions and select an initial assignment function based on whether the original type is f128 or not. We then handle the hard-float case using CCBitConvertToType<>. No functional change. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5269 llvm-svn: 218036
* [mips] Add assembler support for the .set nodsp directive.Toma Tabacu2014-09-173-0/+25
| | | | | | | | | | | | Summary: This directive is used to tell the assembler to reject DSP-specific instructions. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5142 llvm-svn: 217946
* [mips] Improve the error messages given by MipsAsmParser.Toma Tabacu2014-09-161-39/+42
| | | | | | | | | | | | Summary: Changed error messages to be more informative and to resemble other clang/llvm error messages (first letter is lower case, no ending punctuation) and updated corresponding tests. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5065 llvm-svn: 217873
* [mips] Move 32-bit ADDiu instruction alias from Mips64InstrInfo.td to ↵Toma Tabacu2014-09-162-3/+2
| | | | | | | | | | MipsInstrInfo.td. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5244 llvm-svn: 217868
* [mips] Marked the ADDi instruction aliases as not available in Mips32R6 and ↵Toma Tabacu2014-09-162-6/+7
| | | | | | | | | | Mips64R6. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5242 llvm-svn: 217867
* Add mips32 r1 to the list of supported targets for Mips fast-iselReed Kotler2014-09-151-1/+2
| | | | | | | | | | | | | | | | | | | | | Summary: Expand list of supported targets for Mips to include mips32 r1. Previously it only include r2. More patches are coming where there is a difference but in the current patches as pushed upstream, r1 and r2 are equivalent. Test Plan: simplestorefp1.ll add new build bots at mips to test this flavor at both -O0 and -O2 Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5306 llvm-svn: 217821
* [mips] Use early exit in MipsAsmParser::matchCPURegisterName(). NFC.Toma Tabacu2014-09-151-17/+18
| | | | | | | | Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5270 llvm-svn: 217774
* [mips] Marked the DADDiu instruction aliases as MIPS III.Toma Tabacu2014-09-151-4/+4
| | | | | | | | Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5239 llvm-svn: 217770
* [mips][microMIPS] Implement JRADDIUSP instructionZoran Jovanovic2014-09-124-0/+52
| | | | | | Differential Revision: http://reviews.llvm.org/D5046 llvm-svn: 217681
* [mips][microMIPS] Implement BGEZALS and BLTZALS instructionsZoran Jovanovic2014-09-122-0/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D5004 llvm-svn: 217678
* [mips][microMIPS] Implement JALS and JALRS instructions.Zoran Jovanovic2014-09-122-4/+37
| | | | | | Differential Revision: http://reviews.llvm.org/D5003 llvm-svn: 217676
* [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructionsZoran Jovanovic2014-09-123-5/+19
| | | | | | Differential Revision: http://reviews.llvm.org/D5211 llvm-svn: 217675
* Remove a temporary variable and just construct a unique_ptr directly using ↵Craig Topper2014-09-121-9/+6
| | | | | | make_unique. llvm-svn: 217655
* [mips] Remove inverted predicates from MipsSubtarget that were only used by ↵Daniel Sanders2014-09-102-14/+15
| | | | | | | | | | | | | | | | MipsCallingConv.td Summary: No functional change Reviewers: echristo, vmedic Reviewed By: echristo, vmedic Subscribers: echristo, llvm-commits Differential Revision: http://reviews.llvm.org/D5266 llvm-svn: 217494
* [mips] Return an ArrayRef from MipsCC::intArgRegs() and remove ↵Daniel Sanders2014-09-102-24/+19
| | | | | | | | | | | | | | | | MipsCC::numIntArgRegs() Summary: No functional change. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5265 llvm-svn: 217485
* [MIPS] Add aliases for sync instruction used by Octeon CPUKai Nacke2014-09-101-0/+6
| | | | | | | | | This commit adds aliases for the sync instruction (synciobdma, syncs, syncw, syncws) which are used by the Octeon CPU. Reviewed by D. Sanders llvm-svn: 217477
* [mips] Add assembler support for .set mips0 directive.Toma Tabacu2014-09-093-0/+21
| | | | | | | | | | | | | | | | | | Summary: This directive is used to reset the assembler options to their initial values. Assembly programmers use it in conjunction with the ".set mipsX" directives. This patch depends on the .set push/pop directive (http://reviews.llvm.org/D4821). Contains work done by Matheus Almeida. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4957 llvm-svn: 217438
* [mips] Move MipsTargetLowering::MipsCC::regSize() to ↵Daniel Sanders2014-09-093-32/+32
| | | | | | | | | | | | | | | | | | | | MipsSubtarget::getGPRSizeInBytes() Summary: The GPR size is more a property of the subtarget than that of the ABI so move this information to the MipsSubtarget. No functional change. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5009 llvm-svn: 217436
* [mips] Don't cache IsO32 and IsFP64 in MipsTargetLowering::MipsCCDaniel Sanders2014-09-092-23/+28
| | | | | | | | | | | | | | | | | Summary: Use a MipsSubtarget reference instead. No functional change. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5008 llvm-svn: 217434
* [mips] Add assembler support for .set push/pop directive.Toma Tabacu2014-09-093-17/+95
| | | | | | | | | | | | | | | Summary: These directives are used to save the current assembler options (in the case of ".set push") and restore the previously saved options (in the case of ".set pop"). Contains work done by Matheus Almeida. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4821 llvm-svn: 217432
* [mips] Change Feature-related types from unsigned to uint64_t in ↵Toma Tabacu2014-09-051-2/+2
| | | | | | | | | | | | | | MipsAsmParser. No functional changes. Summary: Found a couple of cases where unsigned was still being used. These two should be the last ones in the (entire) Mips backend. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5028 llvm-svn: 217257
* [mips] Marked the Trap-on-Condition instructions as Mips IIDaniel Sanders2014-09-051-14/+20
| | | | | | | | | | | | Patch by Vasileios Kalintiris. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5173 llvm-svn: 217255
* [mips] Rename data members and member functions in MipsAssemblerOptions.Toma Tabacu2014-09-051-14/+14
| | | | | | | | | | | | Summary: Use the naming convention from the LLVM Coding Standards. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4972 llvm-svn: 217254
* [mips] Rename MipsAsmParser functions to conform to the LLVM Coding ↵Toma Tabacu2014-09-044-64/+64
| | | | | | | | | | | | | | Standards. No functional changes. Summary: There are still some functions which should be renamed, but they are inherited from the generic MC classes. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5068 llvm-svn: 217145
* Make some helpers static or move into the llvm namespace.Benjamin Kramer2014-09-032-4/+3
| | | | llvm-svn: 217077
* [FastISel][tblgen] Rename tblgen generated FastISel functions. NFC.Juergen Ributzka2014-09-031-1/+1
| | | | | | | | | | This is the final round of renaming. This changes tblgen to emit lower-case function names for FastEmitInst_* and FastEmit_*, and updates all its uses in the source code. Reviewed by Eric llvm-svn: 217075
* [FastISel] Rename public visible FastISel functions. NFC.Juergen Ributzka2014-09-031-5/+5
| | | | | | | | | | | | | | | | | | | | | This commit renames the following public FastISel functions: LowerArguments -> lowerArguments SelectInstruction -> selectInstruction TargetSelectInstruction -> fastSelectInstruction FastLowerArguments -> fastLowerArguments FastLowerCall -> fastLowerCall FastLowerIntrinsicCall -> fastLowerIntrinsicCall FastEmitZExtFromI1 -> fastEmitZExtFromI1 FastEmitBranch -> fastEmitBranch UpdateValueMap -> updateValueMap TargetMaterializeConstant -> fastMaterializeConstant TargetMaterializeAlloca -> fastMaterializeAlloca TargetMaterializeFloatZero -> fastMaterializeFloatZero LowerCallTo -> lowerCallTo Reviewed by Eric llvm-svn: 217074
* Add override to overriden virtual methods, remove virtual keywords.Benjamin Kramer2014-09-031-2/+2
| | | | | | No functionality change. Changes made by clang-tidy + some manual cleanup. llvm-svn: 217028
* Reinstate "Nuke the old JIT."Eric Christopher2014-09-0215-862/+9
| | | | | | | | Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reinstates commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 216982
* Fix left shifts of negative values in MipsDisassembler.Alexey Samsonov2014-09-021-15/+15
| | | | | | This bug was reported by UBSan. llvm-svn: 216920
* Fix some cases where StringRef was being passed by const reference. Remove ↵Craig Topper2014-08-305-8/+8
| | | | | | const from some other StringRefs since its implicitly const already. llvm-svn: 216820
* Fix typos in comments, NFCRobin Morisset2014-08-291-2/+2
| | | | | | | | | | | | | | Summary: Just fixing comments, no functional change. Test Plan: N/A Reviewers: jfb Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D5130 llvm-svn: 216784
* [mips] Don't use odd-numbered float registers for double arguments for fastccSasa Stankovic2014-08-221-2/+6
| | | | | | | | calling convention if FP is 64-bit and +nooddspreg is used. Differential Revision: http://reviews.llvm.org/D4981.diff llvm-svn: 216262
* [mips] Add assembler support for .set arch=x directive.Toma Tabacu2014-08-193-0/+48
| | | | | | | | | | | | | | | | | | Summary: This directive is similar to ".set mipsX". It is used to change the CPU target of the assembler, enabling it to accept instructions for a specific CPU. This patch only implements the r4000 CPU (which is treated internally as generic mips3) and the generic ISAs. Contains work done by Matheus Almeida. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4884 llvm-svn: 215978
* TableGen: allow use of uint64_t for available features mask.Tim Northover2014-08-181-3/+3
| | | | | | | | | | ARM in particular is getting dangerously close to exceeding 32 bits worth of possible subtarget features. When this happens, various parts of MC start to fail inexplicably as masks get truncated to "unsigned". Mostly just refactoring at present, and there's probably no way to test. llvm-svn: 215887
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