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* Split generated asm mnemonic matching table into a separate table for each ↵Craig Topper2013-07-241-1/+1
| | | | | | | | asm variant. This removes the need to store the asm variant in each row of the single table that existed before. Shaves ~16K off the size of X86AsmParser.o. llvm-svn: 187026
* [mips] Fix MipsAsmParser::parseCCRRegs.Akira Hatanaka2013-07-221-17/+10
| | | | | | | | Enable parsing all 32 floating point control registers $0-31 and stop trying to parse floating point condition code register $fcc0. Also, return ParseFail if the operand being parsed is not in the expected format. llvm-svn: 186861
* [mips] Use ADDu instead of OR to copy general purpose registers. Also, deleteAkira Hatanaka2013-07-223-12/+5
| | | | | | | the InstAlias pattern which maps "move" to OR to resolve ambiguity in MatchTable. llvm-svn: 186855
* [mips] Delete MFC1_FT_CCR, MTC1_FT_CCR and MOVCCRToCCR.Akira Hatanaka2013-07-192-15/+2
| | | | | | No functionality change. llvm-svn: 186642
* This patch extends mips register parsing methods to allow indexed register ↵Vladimir Medic2013-07-181-0/+12
| | | | | | parsing. The corresponding test cases are added to the patch. llvm-svn: 186567
* [mips] Use "foreach" loop to make register definitions more concise.Akira Hatanaka2013-07-171-80/+9
| | | | llvm-svn: 186528
* This patch checks for valid mnemonics at the beginning of parseInstruction ↵Vladimir Medic2013-07-171-0/+5
| | | | | | method, thus giving the user the right error message for non-existing instructions. llvm-svn: 186512
* Implement eret and deret(return from exception) instructions for Mips. Test ↵Vladimir Medic2013-07-172-0/+21
| | | | | | examples are given. llvm-svn: 186507
* Test commit to verify write access.Juergen Ributzka2013-07-161-0/+1
| | | | llvm-svn: 186429
* Fixing a buildbot failure:unused function.Vladimir Medic2013-07-161-14/+0
| | | | llvm-svn: 186403
* This patch represents Mips utilization of r186388 code that alows asm ↵Vladimir Medic2013-07-164-270/+242
| | | | | | matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient. llvm-svn: 186397
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-142-5/+5
| | | | | | size. llvm-svn: 186274
* [mips] Implement MipsTargetMachine::getInstrItineraryData().Akira Hatanaka2013-07-123-2/+9
| | | | llvm-svn: 186227
* [mips] Add instruction itinerary classes for mult, seb and slt instructions.Akira Hatanaka2013-07-123-13/+16
| | | | llvm-svn: 186222
* Add support for Mips break and syscall insructions. The corresponding test ↵Vladimir Medic2013-07-122-0/+49
| | | | | | cases are added. llvm-svn: 186151
* Reverting commit r185999 due to buildboot failure.Vladimir Medic2013-07-102-49/+0
| | | | llvm-svn: 186000
* Add support for Mips break and syscall insructions. The corresponding test ↵Vladimir Medic2013-07-102-0/+49
| | | | | | cases are added. llvm-svn: 185999
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-041-5/+0
| | | | | | These exception-related opcodes are not used any longer. llvm-svn: 185625
* Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid ↵Craig Topper2013-07-041-1/+1
| | | | | | specifying the vector size. llvm-svn: 185606
* Revert r185595-185596 which broke buildbots.Jakob Stoklund Olesen2013-07-041-0/+5
| | | | | | | Revert "Simplify landing pad lowering." Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes." llvm-svn: 185600
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-031-5/+0
| | | | | | These exception-related opcodes are not used any longer. llvm-svn: 185596
* Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid ↵Craig Topper2013-07-032-3/+3
| | | | | | specifying the vector size. llvm-svn: 185540
* [mips] Add new InstrItinClasses for move from/to coprocessor instructions andAkira Hatanaka2013-07-024-56/+70
| | | | | | | | floating point loads and stores. No changes in functionality. llvm-svn: 185399
* [mips] Reverse the order of source operands of shift and rotate instructions ↵Akira Hatanaka2013-07-012-8/+8
| | | | | | | | | | that have three register operands. No intended functionality changes. llvm-svn: 185376
* [mips] Increase the number of floating point control registers available to 32.Akira Hatanaka2013-07-011-4/+9
| | | | | | | Create a dedicated register class for floating point condition code registers and move FCC0 from register class CCR to the new register class. llvm-svn: 185373
* [Mips Disassembler] Have the DecodeCCRRegisterClass function use the getRegChad Rosier2013-06-261-1/+4
| | | | | | | function to lookup the proper tablegen'ed register enumeration. Previously, it was using the encoded value directly. llvm-svn: 185026
* [mips] Do not emit ".option pic0" if target is mips64.Akira Hatanaka2013-06-261-1/+1
| | | | llvm-svn: 185012
* [mips] Improve code generation for constant multiplication using shifts, ↵Akira Hatanaka2013-06-261-0/+54
| | | | | | | | adds and subs. llvm-svn: 185011
* This patch introduces RegisterOperand class into Mips FPU instruction ↵Vladimir Medic2013-06-243-87/+157
| | | | | | definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser. llvm-svn: 184716
* The getRegForInlineAsmConstraint function should only accept MVT value types.Chad Rosier2013-06-222-2/+2
| | | | llvm-svn: 184642
* Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU ↵Vladimir Medic2013-06-201-48/+58
| | | | | | registers. llvm-svn: 184411
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-193-5/+8
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184360
* The RenderMethod field in RegisterOperand class sets the name of the method ↵Vladimir Medic2013-06-192-19/+10
| | | | | | on the target specific operand to call to add the target specific operand to an MCInst. This patch defines RenderMethod for mips RegisterOperand classes and removes redundant code from MipsAsmParser.cpp llvm-svn: 184292
* Mips ELF: Mark object file as ABI compliant Jack Carter2013-06-182-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When producing objects that are abi compliant we are marking neither the object file nor the assembly file correctly and thus generate warnings. We need to set the EF_CPIC flag in the ELF header when generating direct object. Note that the warning is only generated when compiling without PIC. When compiling with clang the warning will be suppressed by supplying: -Wa,-mno-shared -Wa,-call_nonpic Also the following directive should also be added: .option pic0 when compiling without PIC, This eliminates the need for supplying: -mno-shared -call_nonpic on the assembler command line. Patch by Douglas Gilmore llvm-svn: 184220
* Use pointers to the MCAsmInfo and MCRegInfo.Bill Wendling2013-06-184-12/+12
| | | | | | | | | Someone may want to do something crazy, like replace these objects if they change or something. No functionality change intended. llvm-svn: 184175
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE ↵David Blaikie2013-06-164-25/+0
| | | | | | | | | | MachineInstrs Frame index handling is now target-agnostic, so delete the target hooks for creation & asm printing of target-specific addressing in DBG_VALUEs and any related functions. llvm-svn: 184067
* Mips: Remove global set.Benjamin Kramer2013-06-132-57/+68
| | | | | | Backends shouldn't retain any global state. No functionality change. llvm-svn: 183927
* Fix CMakeLists.Akira Hatanaka2013-06-111-0/+1
| | | | llvm-svn: 183804
* [mips] Add an IR transformation pass that optimizes calls to sqrt.Akira Hatanaka2013-06-113-1/+177
| | | | | | | | | The pass emits a call to sqrt that has attribute "read-none". This call will be converted to an ISD::FSQRT node during DAG construction, which will turn into a mips native sqrt instruction. llvm-svn: 183802
* [mips] Use function TargetInstrInfo::getRegClass.Akira Hatanaka2013-06-112-6/+9
| | | | | | No functionality changes. llvm-svn: 183767
* Fix a regression I introduced when I expanded the complex pseudos inReed Kotler2013-06-092-9/+10
| | | | | | | | | the Mips16 port. A few of the psuedos could either take signed or unsigned arguments and I did not distinguish the case and improperly rejected some valid cases that the assembler had previously accepted when they were pure pseudos that expanded as assembly instructions. llvm-svn: 183633
* [mips] Use a helper function which compares the size of the source andAkira Hatanaka2013-06-082-8/+21
| | | | | | | | destination operands of an instruction. No functionality changes. llvm-svn: 183596
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-0711-40/+67
| | | | | | the internals of TargetMachine could change. llvm-svn: 183493
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-063-5/+5
| | | | | | | Caching it as a pointer allows us to reset it if the TargetMachine object changes. llvm-svn: 183361
* [mips] brcond + setgt/setugt instruction selection patterns.Akira Hatanaka2013-06-051-0/+4
| | | | llvm-svn: 183334
* Test commit for user vmedic, to verify commit access. One line of comment is ↵Vladimir Medic2013-06-041-1/+1
| | | | | | added to MipsAsmParser.cpp. llvm-svn: 183215
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-311-10/+10
| | | | | | | This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. llvm-svn: 183061
* [mips] Big-endian code generation for atomic instructions.Akira Hatanaka2013-05-311-2/+16
| | | | | | Patch by Jyun-Yan You. llvm-svn: 182984
* Order CALLSEQ_START and CALLSEQ_END nodes.Andrew Trick2013-05-291-2/+2
| | | | | | | | | | | | Fixes PR16146: gdb.base__call-ar-st.exp fails after pre-RA-sched=source fixes. Patch by Xiaoyi Guo! This also fixes an unsupported dbg.value test case. Codegen was previously incorrect but the test was passing by luck. llvm-svn: 182885
* Mips assembler: Improve set register alias handlingJack Carter2013-05-281-5/+28
| | | | | | | | | | | | | | | | This patch solves the problem of numeric register values not being accepted: ../set_alias.s:1:11: error: expected valid expression after comma .set r4,$4 ^ The parsing of .set directive is changed and handling of symbols in code as well to enable this feature. The test example is added. Patch by Vladimir Medic llvm-svn: 182807
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