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* Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.Patrik Hagglund2012-12-111-3/+3
| | | | | | | | | Accordingly, add helper funtions getSimpleValueType (in parallel to getValueType) in SDValue, SDNode, and TargetLowering. This is the first, in a series of patches. llvm-svn: 169837
* [CMake] Remove dependencies to intrinsics_gen I introduced in r169724.NAKAMURA Takumi2012-12-111-1/+1
| | | | llvm-svn: 169819
* Some enhancements for memcpy / memset inline expansion.Evan Cheng2012-12-102-2/+5
| | | | | | | | | | | | | | | | | | | | | 1. Teach it to use overlapping unaligned load / store to copy / set the trailing bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies. 2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g. x86 and ARM. 3. When memcpy from a constant string, do *not* replace the load with a constant if it's not possible to materialize an integer immediate with a single instruction (required a new target hook: TLI.isIntImmLegal()). 4. Use unaligned load / stores more aggressively if target hooks indicates they are "fast". 5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8. Also increase the threshold to something reasonable (8 for memset, 4 pairs for memcpy). This significantly improves Dhrystone, up to 50% on ARM iOS devices. rdar://12760078 llvm-svn: 169791
* [mips] Set HWEncoding field of registers. Use delete functionAkira Hatanaka2012-12-105-130/+30
| | | | | | getMipsRegisterNumbering and use MCRegisterInfo::getEncodingValue instead. llvm-svn: 169760
* [CMake] Update dependencies to intrinsics_gen corresponding to r169711.NAKAMURA Takumi2012-12-101-1/+1
| | | | llvm-svn: 169724
* Use the new MIBundleBuilder class in the Mips target.Jakob Stoklund Olesen2012-12-072-18/+26
| | | | | | This is the preferred way of creating bundled machine instructions. llvm-svn: 169585
* [mips] Delete nodes and instructions for dynamic alloca that are no longer inAkira Hatanaka2012-12-073-23/+0
| | | | | | use. llvm-svn: 169580
* [mips] Shorten predicate name.Akira Hatanaka2012-12-075-105/+105
| | | | llvm-svn: 169579
* [mips] Delete unused sub-target features.Akira Hatanaka2012-12-073-15/+2
| | | | llvm-svn: 169578
* [mips] Remove unnecessary predicates.Akira Hatanaka2012-12-073-4/+4
| | | | llvm-svn: 169577
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-045-6/+6
| | | | | | | | | | missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
* Classic JIT is still being supported by MIPS, along with MCJIT.Akira Hatanaka2012-12-033-11/+24
| | | | | | | | | This change adds endian-awareness to MipsJITInfo and emitWordLE in MipsCodeEmitter has become emitWord now to support both endianness. Patch by Petar Jovanovic. llvm-svn: 169177
* Functions in MipsCodeEmitter.cpp that expand unaligned loads/stores are deadAkira Hatanaka2012-12-031-103/+0
| | | | | | | | code. Removing it. Patch by Petar Jovanovic. llvm-svn: 169174
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-0323-101/+102
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Switch LLVM_USE_RVALUE_REFERENCES to LLVM_HAS_RVALUE_REFERENCES.Chandler Carruth2012-11-301-1/+1
| | | | | | | | | | | | | | Rationale: 1) This was the name in the comment block. ;] 2) It matches Clang's __has_feature naming convention. 3) It matches other compiler-feature-test conventions. Sorry for the noise. =] I've also switch the comment block to use a \brief tag and not duplicate the name. llvm-svn: 168996
* Mips direct object xgot supportJack Carter2012-11-214-1/+45
| | | | | | | | | | | | | | This patch provides support for the MIPS relocations: *) R_MIPS_GOT_HI16 *) R_MIPS_GOT_LO16 *) R_MIPS_CALL_HI16 *) R_MIPS_CALL_LO16 These are used for large GOT instruction sequences. Contributer: Jack Carter llvm-svn: 168471
* [mips] Generate big GOT code.Akira Hatanaka2012-11-215-3/+25
| | | | llvm-svn: 168460
* [mips] Simplify lowering functions in MipsISelLowering.cpp by using the helperAkira Hatanaka2012-11-211-148/+32
| | | | | | functions added in r168456. llvm-svn: 168458
* [mips] Add helper functions that create nodes for computing address.Akira Hatanaka2012-11-211-0/+65
| | | | llvm-svn: 168456
* [mips] Add command line option "-mxgot".Akira Hatanaka2012-11-211-0/+4
| | | | llvm-svn: 168455
* [mips] When a node which loads from a GOT is created, pass a MachinePointerInfoAkira Hatanaka2012-11-211-4/+6
| | | | | | referring to a GOT entry. llvm-svn: 168453
* [mips] Add target operand flag enums for big GOT relocations.Akira Hatanaka2012-11-211-1/+7
| | | | llvm-svn: 168450
* Initial implementation of MipsTargetLowering::isLegalAddressingMode.Akira Hatanaka2012-11-172-0/+22
| | | | llvm-svn: 168230
* [mips] Fix delay slot filler so that instructions with register operand $1 areAkira Hatanaka2012-11-161-17/+34
| | | | | | allowed in branch delay slot. llvm-svn: 168131
* [mips] Add predicate HasFPIdx for floating-point indexed load instructionAkira Hatanaka2012-11-156-11/+16
| | | | | | support and use it in place of HasMips32r2Or64. llvm-svn: 168089
* Add assertions in MipsLongBranch which check the size of basic blocks.Akira Hatanaka2012-11-151-1/+7
| | | | llvm-svn: 168078
* [mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node.Akira Hatanaka2012-11-072-0/+27
| | | | | | Patch by Sasa Stankovic. llvm-svn: 167548
* Delete MipsFunctionInfo::NextStackOffset. No functionality change intended. Akira Hatanaka2012-11-072-10/+6
| | | | llvm-svn: 167546
* [mips] Set flag neverHasSideEffects flag on floating point conversionAkira Hatanaka2012-11-032-6/+11
| | | | | | instructions. llvm-svn: 167348
* [mips] Set flag isAsCheapAsAMove flag on instruction LUi.Akira Hatanaka2012-11-031-1/+1
| | | | llvm-svn: 167345
* [mips] Stop reserving register AT and use register scavenger when a scratchAkira Hatanaka2012-11-035-13/+47
| | | | | | register is needed. llvm-svn: 167341
* [mips] Do not reserve all 64-bit registers, but only the ones which need to beAkira Hatanaka2012-11-021-8/+4
| | | | | | | reserved. Without this fix, RegScavenger::getRegsAvailable incorrectly returns an empty set of integer registers. llvm-svn: 167335
* [mips] Use register number instead of name to print register $AT.Akira Hatanaka2012-11-021-2/+2
| | | | llvm-svn: 167315
* [mips] Add function MipsFrameLowering::estimateStackSize.Akira Hatanaka2012-11-022-0/+37
| | | | | | | This function estimates stack size and will be called before PrologEpilogInserter scans the callee-saved registers. llvm-svn: 167313
* [mips] Add member field MipsFunctionInfo::IncomingArgSize which holds the sizeAkira Hatanaka2012-11-022-0/+7
| | | | | | of the incoming argument area. llvm-svn: 167312
* [mips] Delete MipsFunctionInfo::EmitNOAT. Unconditionally print directiveAkira Hatanaka2012-11-025-16/+3
| | | | | | | "set .noat" so that the assembler doesn't issue warnings when register $AT is used. llvm-svn: 167310
* [mips] Set isAsCheapAsAMove flag on ADDiu and DADDiu, which enablesAkira Hatanaka2012-10-312-2/+7
| | | | | | re-materialization of immediate loads. llvm-svn: 167153
* Implement ADJCALLSTACKUP and ADJCALLSTACKDOWNReed Kotler2012-10-316-9/+67
| | | | llvm-svn: 167107
* [mips] Allow tail-call optimization for vararg functions and functions whichAkira Hatanaka2012-10-302-15/+20
| | | | | | use the caller's stack. llvm-svn: 167048
* Add code for saving formal argument information to MipsFunctionInfo. ThisAkira Hatanaka2012-10-302-0/+13
| | | | | | | information will be used by IsEligibleForTailCallOptimization to determine whether a call can be tail-call optimized. llvm-svn: 167043
* Add definition of function MipsTargetLowering::passArgOnStack which emits nodesAkira Hatanaka2012-10-302-0/+22
| | | | | | for passing a function call argument on a stack. llvm-svn: 167041
* Do not do tail-call optimization if target is mips16.Akira Hatanaka2012-10-301-0/+4
| | | | llvm-svn: 167039
* Change mips16 delay slot jumps to non delay slot forms by default.Reed Kotler2012-10-302-3/+10
| | | | | | | | We will make them delay slot forms if there is something that can be placed in the delay slot during a separate pass. Mips16 extended instructions cannot be placed in delay slots. llvm-svn: 166990
* Implement patterns for extloadi8 and extloadi16Reed Kotler2012-10-291-0/+4
| | | | llvm-svn: 166960
* Expand all atomic ops for mips16.Reed Kotler2012-10-291-2/+23
| | | | llvm-svn: 166935
* Implement brind operator for mips16.Reed Kotler2012-10-281-0/+19
| | | | llvm-svn: 166903
* Remove TargetELFWriterInfo.Rafael Espindola2012-10-285-158/+1
| | | | | | All the credit goes to Jan Voung for noticing it was dead! llvm-svn: 166902
* This patch is for the implementation of mips16 complex pattern addr16.Reed Kotler2012-10-287-48/+276
| | | | | | | | | | | | | | | | | | | | | Previously mips16 was sharing the pattern addr which is used for mips32 and mips64. This had a number of problems: 1) Storing and loading byte and halfword quantities for mips16 has particular problems due to the primarily non mips16 nature of SP. When we must load/store byte/halfword stack objects in a function, we must create a mips16 alias register for SP. This functionality is tested in stchar.ll. 2) We need to have an FP register under certain conditions (such as dynamically sized alloca). We use mips16 register S0 for this purpose. In this case, we also use this register when accessing frame objects so this issue also affects the complex pattern addr16. This functionality is tested in alloca16.ll. The Mips16InstrInfo.td has been updated to use addr16 instead of addr. The complex pattern C++ function for addr has been copied to addr16 and updated to reflect the above issues. llvm-svn: 166897
* Implement MipsHi for mips16Reed Kotler2012-10-271-2/+8
| | | | llvm-svn: 166852
* [mips] Do not tail-call optimize vararg functions or functions with byvalAkira Hatanaka2012-10-272-9/+8
| | | | | | | | arguments. This is rather conservative and should be fixed later to be more aggressive. llvm-svn: 166851
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