summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Mips
Commit message (Collapse)AuthorAgeFilesLines
* [mips] Fix comment to respect 80 chars per line; NFCSimon Dardis2016-12-131-6/+6
| | | | llvm-svn: 289530
* [mips] Fix compact branch hazard detectionSimon Dardis2016-12-131-22/+42
| | | | | | | | | | | | | In certain cases it is possible that transient instructions such as %reg = IMPLICIT_DEF as a single instruction in a basic block to reach the MipsHazardSchedule pass. This patch teaches MipsHazardSchedule to properly look through such cases. Reviewers: vkalintiris, zoran.jovanovic Differential Revision: https://reviews.llvm.org/D27209 llvm-svn: 289529
* [mips] For PIC code convert unconditional jump to unconditional branchSimon Atanasyan2016-12-121-0/+11
| | | | | | | | | | | | Unconditional branch uses relative addressing which is the right choice in case of position independent code. This is a fix for the bug: https://dmz-portal.mips.com/bugz/show_bug.cgi?id=2445 Differential revision: https://reviews.llvm.org/D27483 llvm-svn: 289448
* [mips] Eliminate else-after-return. NFCSimon Atanasyan2016-12-101-4/+3
| | | | llvm-svn: 289331
* [mips][ias] N32/N64 must not sort the relocation table.Simon Dardis2016-12-051-0/+7
| | | | | | | | | | | | Doing so changes the evaluation order for relocation composition. Patch By: Daniel Sanders Reviewers: vkalintiris, atanasyan Differential Revision: https://reviews.llvm.org/D26401 llvm-svn: 288666
* IR: Change the gep_type_iterator API to avoid always exposing the "current" ↵Peter Collingbourne2016-12-021-1/+1
| | | | | | | | | | | | | type. Instead, expose whether the current type is an array or a struct, if an array what the upper bound is, and if a struct the struct type itself. This is in preparation for a later change which will make PointerType derive from Type rather than SequentialType. Differential Revision: https://reviews.llvm.org/D26594 llvm-svn: 288458
* Move FrameInstructions from MachineModuleInfo to MachineFunctionMatthias Braun2016-11-302-10/+10
| | | | | | | | | | | This is per function data so it is better kept at the function instead of the module. This is a necessary step to have machine module passes work properly. Differential Revision: https://reviews.llvm.org/D27185 llvm-svn: 288291
* [mips] Correct jal expansion for local symbols in .local directives.Simon Dardis2016-11-251-1/+2
| | | | | | | | | | | | | | | | | This patch corrects the behaviour of code such as: .local foo jal foo foo: to use the correct jal expansion when writing ELF files. Patch by: Daniel Sanders Reviewers: zoran.jovanovic, seanbruno, vkalintiris Differential Revision: https://reviews.llvm.org/D24722 llvm-svn: 287918
* [mips] seb, seh instruction aliasesSimon Dardis2016-11-223-0/+12
| | | | | | | | | | Add the single operand form. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D26961 llvm-svn: 287681
* [mips] Add support for unaligned load/store macros.Vasileios Kalintiris2016-11-222-84/+111
| | | | | | | | Add missing unaligned store macros (ush/usw) and fix the exisiting implementation of the unaligned load macros in order to generate identical expansions with the GNU assembler. llvm-svn: 287646
* [mips] seq macro supportSimon Dardis2016-11-212-0/+110
| | | | | | | | | | | | | | This patch adds the seq macro. This partially resolves PR/30381. Thanks to Sean Bruno for reporting the issue! Reviewers: zoran.jovanovic, vkalintiris, seanbruno Differential Revision: https://reviews.llvm.org/D24607 llvm-svn: 287573
* [mips] Restrict tail call optimizationSimon Dardis2016-11-201-4/+13
| | | | | | | | | | | | The tail call optimization was being used without proper consideration of ABI requirements for saving and restoring the GP. This patch restricts tail call optimization to functions within the same translation unit. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D24763 llvm-svn: 287505
* [mips][msa] Implement f16 supportSimon Dardis2016-11-184-0/+418
| | | | | | | | | | | | | | | The MIPS MSA ASE provides instructions to convert to and from half precision floating point. This patch teaches the MIPS backend to treat f16 as a legal type and how to promote such values to f32 for the usual set of operations. As a result of this, the fexup[lr].w intrinsics no longer crash LLVM during type legalization. Reviewers: zoran.jovanvoic, vkalintiris Differential Revision: https://reviews.llvm.org/D26398 llvm-svn: 287349
* Fix spelling mistakes in MIPS target comments. NFC.Simon Pilgrim2016-11-183-4/+4
| | | | | | Identified by Pedro Giffuni in PR27636. llvm-svn: 287338
* [mips] Fix unsigned/signed type errorSimon Dardis2016-11-161-3/+3
| | | | | | | | | | | | | | | MipsFastISel uses a a class to represent addresses with a signed member to represent the offset. MipsFastISel::emitStore, emitLoad and computeAddress all treated the offset as being positive. In cases where the offset was actually negative and a frame pointer was used, this would cause the constant synthesis routine to crash as it would generate an unexpected instruction sequence when frame indexes are replaced. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D26192 llvm-svn: 287099
* [mips] not instruction aliasSimon Dardis2016-11-162-0/+5
| | | | | | | | | | | This patch adds the single operand form of the not alias to microMIPS and MIPS along with additional tests. This partially resolves PR/30381. Thanks to Sean Bruno for reporting the issue! llvm-svn: 287097
* Introduce TLI predicative for base-relative Jump Tables.Joerg Sonnenberger2016-11-152-37/+5
| | | | | | | | | | | For 64bit ABIs it is common practice to use relative Jump Tables with potentially different relocation bases. As the logic for the jump table itself doesn't depend on the relocation base, make it easier for targets to use the generic logic. Start by dropping the now redundant MIPS logic. Differential Revision: https://reviews.llvm.org/D26578 llvm-svn: 286951
* Revert: r286868 - Test commitDaniel Sanders2016-11-141-1/+0
| | | | llvm-svn: 286869
* Test commitDaniel Sanders2016-11-141-0/+1
| | | | llvm-svn: 286868
* [mips] Always run the MipsOptimizePICCall pass.Vasileios Kalintiris2016-11-021-8/+1
| | | | | | | | | | | | | Summary: Remove this pass from addMachineSSAOptimization() and register it unconditionally in through addPreRegAlloc(). This pass is required for generating correct PIC calls. Reviewers: sdardis Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26036 llvm-svn: 285814
* [TableGen] Move OperandMatchResultTy enum to MCTargetAsmParser.hAlex Bradbury2016-11-011-10/+10
| | | | | | | | | | | | | | | As it stands, the OperandMatchResultTy is only included in the generated header if there is custom operand parsing. However, almost all backends make use of MatchOperand_Success and friends from OperandMatchResultTy for e.g. parseRegister. This is a pain when starting an AsmParser for a new backend that doesn't yet have custom operand parsing. Move the enum to MCTargetAsmParser.h. This patch is a prerequisite for D23563 Differential Revision: https://reviews.llvm.org/D23496 llvm-svn: 285705
* [mips] Do not allow -opt-bisect-limit to skip the PIC call optimization pass.Vasileios Kalintiris2016-10-271-3/+0
| | | | | | | | | | | | | | r282428 added the MipsOptimizePICCall as an opt-in pass that can be skipped when using the -opt-bisect-limit option. However, this pass is needed because it generates code that conforms to the o32 ABI specification by using the $t9 register for PIC calls with JALR instructions. This bug was exposed by the fact that skipFunction() also checks for the "optnone" attribute. This caused functions with that attribute to break the requirements of the o32 ABI. llvm-svn: 285305
* Target: Change various section classifiers in TargetLoweringObjectFile to ↵Peter Collingbourne2016-10-243-25/+27
| | | | | | | | | | | | | | | | take a GlobalObject. These functions are about classifying a global which will actually be emitted, so it does not make sense for them to take a GlobalValue which may for example be an alias. Change the Mach-O object writer and the Hexagon, Lanai and MIPS backends to look through aliases before using TargetLoweringObjectFile interfaces. These are functional changes but all appear to be bug fixes. Differential Revision: https://reviews.llvm.org/D25917 llvm-svn: 285006
* [mips] synci microMIPS instruction definition.Simon Dardis2016-10-243-3/+15
| | | | | | | | | | | | | Add synci to the microMIPS instruction definitions, mark the MIPS sync & synci as not being part of microMIPS. This does not cover the sync instruction alias, as that will be handled with a different patch. Add sync to the valid tests for microMIPS. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D25795 llvm-svn: 284962
* [mips][ias] Handle more complicated expressions for memory operandsSimon Dardis2016-10-181-2/+54
| | | | | | | | | | | | | | | | This patch teaches ias for mips to handle expressions such as (8*4)+(8*31)($sp). Such expression typically occur from the expansion of multiple macro definitions. This partially resolves PR/30383. Thanks to Sean Bruno for reporting the issue! Reviewers: zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D24667 llvm-svn: 284485
* [mips] Fix sync instruction definitionSimon Dardis2016-10-182-2/+8
| | | | | | | | | | | | | | | | | | | | | | | The 'sync' instruction for MIPS was defined in MIPS-II as taking no operands. MIPS32 extended the define of 'sync' as taking an optional unsigned 5 bit immediate. This patch correct the definition of sync so that it is accepted with an operand of 0 or no operand for MIPS-II to MIPS-V, and a 5 bit unsigned immediate for MIPS32 and later revisions. Additionally a clear error is given when the MIPS32 version of sync is used when targeting pre MIPS32. This partially resolves PR/30714. Thanks to Daniel Sanders for reporting this issue! Reveiwers: vkalintiris Differential Revision: https://reviews.llvm.org/D25672 llvm-svn: 284483
* [mips] Macro expansion for ld, sd for O32Simon Dardis2016-10-182-0/+106
| | | | | | | | | | | | | | | | | | | | | | ld and sd when assembled for the O32 ABI expand to a pair of 32 bit word loads or stores using the specified source or destination register and the next register. This patch does not add support for the cases where the offset is greater than a 16 bit signed immediate as that would lead to a wrong/misleading error message as the assembler would report "instruction requires a CPU feature not currently enabled" for ld & sd for MIPS64 when their offset is not a signed 16 bit number. This fixes PR/29159. Thanks to Sean Bruno for reporting this issue! Reviewers: vkalintiris, seanbruno, zoran.jovanovic Differential Review: https://reviews.llvm.org/D24556 llvm-svn: 284481
* [mips][FastISel] Instantiate the MipsFastISel class only for targets that ↵Vasileios Kalintiris2016-10-182-22/+13
| | | | | | | | | | | | | | | | | | support FastISel. Summary: Instead of instantiating the MipsFastISel class and checking if the target is supported in the overriden methods, we should perform that check before creating the class. This allows us to enable FastISel *only* for targets that truly support it, ie. MIPS32 to MIPS32R5. Reviewers: sdardis Subscribers: ehostunreach, llvm-commits Differential Revision: https://reviews.llvm.org/D24824 llvm-svn: 284475
* [mips] Fix aui/daui/dahi/dati for MIPSR6Simon Dardis2016-10-147-17/+52
| | | | | | | | | | | | For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 284218
* [mips] Add IAS support for dvp, evpSimon Dardis2016-10-134-4/+44
| | | | | | | | | | | | | These instructions were only defined for microMIPSR6 previously. Add definitions for MIPSR6, correct definitions for microMIPSR6, flag these instructions as having unmodelled side effects (they disable/enable virtual processors) and add missing disassember tests for microMIPSR6. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24291 llvm-svn: 284115
* Revert r283690, "MC: Remove unused entities."Peter Collingbourne2016-10-101-1/+1
| | | | llvm-svn: 283814
* Move the global variables representing each Target behind accessor functionMehdi Amini2016-10-097-38/+56
| | | | | | | | This avoids "static initialization order fiasco" Differential Revision: https://reviews.llvm.org/D25412 llvm-svn: 283702
* MC: Remove unused entities.Peter Collingbourne2016-10-091-1/+1
| | | | llvm-svn: 283691
* Turn cl::values() (for enum) from a vararg function to using C++ variadic ↵Mehdi Amini2016-10-081-2/+1
| | | | | | | | | | | | | | | template The core of the change is supposed to be NFC, however it also fixes what I believe was an undefined behavior when calling: va_start(ValueArgs, Desc); with Desc being a StringRef. Differential Revision: https://reviews.llvm.org/D25342 llvm-svn: 283671
* Target: Remove unused patterns and transforms. NFC.Peter Collingbourne2016-10-073-13/+0
| | | | llvm-svn: 283515
* [mips][ias] fix li macro when values are negated with ~Simon Dardis2016-10-052-6/+34
| | | | | | | | | | | | | | | The integrated assembler evaluates the expressions such as ~0x80000000 to 0xffffffff7fffffff early in the parsing process. This patch adds compatibility with gas so that li loads the expected value (0x7fffffff) in those cases. This only occurs iff all the upper 32bits are set and maintains existing checks by not truncating the result down to 32 bits if any of the the upper bits are not set. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D23399 llvm-svn: 283353
* Recommit: "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-057-19/+43
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
* Revert "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-058-77/+25
| | | | | | | This reverts commit r282485 which contain two patches instead of one. llvm-svn: 283327
* [mips][fastisel] Consider soft-float an unsupported floating point modeSimon Dardis2016-10-041-2/+6
| | | | | | | | | | | Treat soft-float as unsupported for fast-isel. Additionally, ensure we check that lowering f32 arguments also considers the case of soft-float mode. Reviewers: ehostunreach, vkalintiris, zoran.jovanovic Differential Review: https://reviews.llvm.org/D24505 llvm-svn: 283209
* Use StringRef instead of raw pointers in MCAsmInfo/MCInstrInfo APIs (NFC)Mehdi Amini2016-10-011-2/+2
| | | | llvm-svn: 283018
* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-0110-22/+10
| | | | llvm-svn: 283004
* Remove an unnecessary duplicate initialization of TLOF from the MipsEric Christopher2016-09-291-4/+0
| | | | | | | | | | | AsmPrinter. This was reinitializing the Mangler after we moved the Mangler down to TLOF and causing us to have two different unnamed global values accessed with the same name. This should fix the problems on the ubsan tests here: http://lab.llvm.org:8011/builders/clang-cmake-mips/builds/15307 llvm-svn: 282675
* [mips] Disable tail calls temporarilySimon Dardis2016-09-271-1/+1
| | | | | | | | | | Disable tail calls while the remaining bugs are fixed. Enable only for tests. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24912 llvm-svn: 282487
* [mips] Add rsqrt, recip for MIPSSimon Dardis2016-09-278-25/+77
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 282485
* Add optimization bisect support to an optional Mips passAndrew Kaylor2016-09-261-0/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D19513 llvm-svn: 282428
* [mips] LLVM PR/30197 - Tail call incorrectly clobbers arguments for mipsSimon Dardis2016-09-211-1/+3
| | | | | | | | | | | | | | | | | The postRA scheduler performs alias analysis to determine if stores and loads can moved past each other. When a function has more arguments than argument registers for the calling convention used, excess arguments are spilled onto the stack. LLVM by default assumes that argument slots are immutable, unless the function contains a tail call. Without the knowledge of that a function contains a tail call site, stores and loads to fixed stack slots may be re-ordered causing the out-going arguments to clobber the incoming arguments before the incoming arguments are supposed to be dead. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24077 llvm-svn: 282063
* Defer asm errors to post-statement failureNirav Dave2016-09-161-40/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recommitting after fixing AsmParser initialization and X86 inline asm error cleanup. Allow errors to be deferred and emitted as part of clean up to simplify and shorten Assembly parser code. This will allow error messages to be emitted in helper functions and be modified by the caller which has better context. As part of this many minor cleanups to the Parser: * Unify parser cleanup on error * Add Workaround for incorrect return values in ParseDirective instances * Tighten checks on error-signifying return values for parser functions and fix in-tree TargetParsers to be more consistent with the changes. * Fix AArch64 test cases checking for spurious error messages that are now fixed. These changes should be backwards compatible with current Target Parsers so long as the error status are correctly returned in appropriate functions. Reviewers: rnk, majnemer Subscribers: aemerson, jyknight, llvm-commits Differential Revision: https://reviews.llvm.org/D24047 llvm-svn: 281762
* [mips] Fix previous revert r281726.Simon Dardis2016-09-161-36/+0
| | | | llvm-svn: 281729
* Revert "[mips] Fix aui/daui/dahi/dati for MIPSR6"Simon Dardis2016-09-167-39/+47
| | | | | | This reverts r281724. Still need dsanders to accept this. llvm-svn: 281726
* [mips] Fix aui/daui/dahi/dati for MIPSR6Simon Dardis2016-09-167-11/+75
| | | | | | | | | | | | For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: vkalintiris, dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 281724
OpenPOWER on IntegriCloud