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* MC: Clean up MCExpr naming. NFC.Jim Grosbach2015-05-307-48/+48
| | | | llvm-svn: 238634
* Rename getOrCreateSymbolData to registerSymbol and return void.Rafael Espindola2015-05-291-1/+1
| | | | | | Another step in merging MCSymbol and MCSymbolData. llvm-svn: 238607
* Pass MCSymbols to the helper functions in MCELF.h.Rafael Espindola2015-05-293-13/+9
| | | | llvm-svn: 238596
* Pass a MCSymbol to needsRelocateWithSymbol.Rafael Espindola2015-05-291-5/+4
| | | | llvm-svn: 238589
* [mips] Remove 2 unused variables in MipsTargetStreamer.cpp. NFC.Toma Tabacu2015-05-291-2/+0
| | | | llvm-svn: 238554
* Remove a trivial forwarding function. NFC.Rafael Espindola2015-05-281-1/+1
| | | | llvm-svn: 238506
* [mips] Add new format for dmtc2/dmfc2 for Octeon CPUs.Kai Nacke2015-05-283-2/+34
| | | | | | | | | | | | | Octeon CPUs use dmtc2 rt,imm16 and dmfcp2 rt,imm16 for the crypto coprocessor. E.g. dmtc2 rt,0x4057 starts calculation of sha-1. I had to introduce a new deconding namespace to avoid a decoding conflict. Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D10083 llvm-svn: 238439
* [Mips64] Add support for MCJIT for MIPS64r2 and MIPS64r6Petar Jovanovic2015-05-281-2/+2
| | | | | | | | | | Add support for resolving MIPS64r2 and MIPS64r6 relocations in MCJIT. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D9667 llvm-svn: 238424
* [mips][microMIPSr6] Implement SEB and SEH instructionsZoran Jovanovic2015-05-273-2/+22
| | | | | | Differential Revision: http://reviews.llvm.org/D9739 llvm-svn: 238333
* [mips][microMIPSr6] Implement BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC ↵Jozef Kolek2015-05-273-7/+89
| | | | | | | | | | | and BNEZALC instructions This patch implements microMIPS32r6 BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC and BNEZALC instructions using mapping. Differential Revision: http://reviews.llvm.org/D10031 llvm-svn: 238325
* Use operator<< instead of print in a few more places.Rafael Espindola2015-05-271-2/+2
| | | | llvm-svn: 238315
* Revert r238190 and r238197: [mips] Make TTypeEncoding indirect to allow ↵Daniel Sanders2015-05-272-9/+1
| | | | | | | | | | .eh_frame to be read-only. This broke the llvm-mips-linux builder and several of our out-of-tree builders. Initial investigations show that the commit probably isn't the problem but reverting anyway while I investigate. llvm-svn: 238302
* Replace getOrCreateSectionData with registerSection.Rafael Espindola2015-05-262-7/+7
| | | | | | There is now no SectionData to be created. llvm-svn: 238208
* Use std::bitset for SubtargetFeatures.Michael Kuperstein2015-05-264-64/+68
| | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
* [mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only.Daniel Sanders2015-05-262-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Following on from r209907 which made personality encodings indirect, do the same for TType encodings. This fixes the case where a try/catch block needs to generate references to, for example, std::exception in the .gcc_except_table. This commit uses DW_EH_PE_sdata8 for N64 as far as is possible at the moment. However, it is possible to end up with DW_EH_PE_sdata4 when a TargetMachine is not available. There's no risk of issues with inconsistency here since the tables are self describing but it does mean there is a small chance of the PC-relative offset being out of range for particularly large programs. Reviewers: petarj Reviewed By: petarj Subscribers: srhines, joerg, tberghammer, llvm-commits Differential Revision: http://reviews.llvm.org/D9669 llvm-svn: 238190
* [Mips] Prefer Twine::utohexstr over utohexstr, saves a string copy.Benjamin Kramer2015-05-231-3/+2
| | | | | | NFC. llvm-svn: 238103
* [opaque pointer type] Allow gep_type_iterator to work with the pointee type ↵David Blaikie2015-05-211-0/+1
| | | | | | | | | | | from the GEP instruction The raw non-instruction/constant form of this is still relying on being able to access the pointee type from a pointer type - those will be cleaned up later. For now, just focus on the cases where the pointee type is easily accessible. llvm-svn: 237958
* Stop forwarding (get|set)Aligment from MCSectionData to MCSection.Rafael Espindola2015-05-212-16/+17
| | | | llvm-svn: 237956
* Move alignment from MCSectionData to MCSection.Rafael Espindola2015-05-218-22/+24
| | | | | | | | | | | | | | | | | | | | | | | | This starts merging MCSection and MCSectionData. There are a few issues with the current split between MCSection and MCSectionData. * It optimizes the the not as important case. We want the production of .o files to be really fast, but the split puts the information used for .o emission in a separate data structure. * The ELF/COFF/MachO hierarchy is not represented in MCSectionData, leading to some ad-hoc ways to represent the various flags. * It makes it harder to remember where each item is. The attached patch starts merging the two by moving the alignment from MCSectionData to MCSection. Most of the patch is actually just dropping 'const', since MCSectionData is mutable, but MCSection was not. llvm-svn: 237936
* Revert r237789 - [mips] The naming convention for private labels is ABI ↵Daniel Sanders2015-05-205-23/+2
| | | | | | | | | dependant. It works, but I've noticed that I missed several callers of createMCAsmInfo() and many don't have a TargetMachine to provide. llvm-svn: 237792
* [mips] The naming convention for private labels is ABI dependant.Daniel Sanders2015-05-205-2/+23
| | | | | | | | | | | | | | | | | Summary: For N32/N64, private labels begin with '.L' but for O32 they begin with '$'. MCAsmInfo now has an initializer function which can be used to provide information from the TargetMachine to control the assembly syntax. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: jfb, sandeep, llvm-commits, rafael Differential Revision: http://reviews.llvm.org/D9821 llvm-svn: 237789
* [mips] [IAS] Factor out .set nomacro warning. NFC.Toma Tabacu2015-05-201-8/+11
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9772 llvm-svn: 237780
* [mips][microMIPSr6] Implement NOR, OR, ORI, XOR and XORI instructionsZoran Jovanovic2015-05-192-7/+22
| | | | | | Differential Revision: http://reviews.llvm.org/D8800 llvm-svn: 237697
* [mips][microMIPSr6] Implement AND and ANDI instructionsZoran Jovanovic2015-05-192-3/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D8772 llvm-svn: 237696
* [mips] Correct and improve special-case shuffle instructions.Daniel Sanders2015-05-196-114/+271
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The documentation writes vectors highest-index first whereas LLVM-IR writes them lowest-index first. As a result, instructions defined in terms of left_half() and right_half() had the halves reversed. In addition to correcting them, they have been improved to allow shuffles that use the same operand twice or in reverse order. For example, ilvev used to accept masks of the form: <0, n, 2, n+2, 4, n+4, ...> but now accepts: <0, 0, 2, 2, 4, 4, ...> <n, n, n+2, n+2, n+4, n+4, ...> <0, n, 2, n+2, 4, n+4, ...> <n, 0, n+2, 2, n+4, 4, ...> One further improvement is that splati.[bhwd] is now the preferred instruction for splat-like operations. The other special shuffles are no longer used for splats. This lead to the discovery that <0, 0, ...> would not cause splati.[hwd] to be selected and this has also been fixed. This fixes the enc-3des test from the test-suite on Mips64r6 with MSA. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9660 llvm-svn: 237689
* [mips][microMIPSr6] Implement DIV, DIVU, MOD and MODU instructionsZoran Jovanovic2015-05-192-5/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D8769 llvm-svn: 237685
* [mips][microMIPSr6] Implement LSA instructionJozef Kolek2015-05-183-2/+31
| | | | | | | | This patch implements LSA instruction using mapping. Differential Revision: http://reviews.llvm.org/D8919 llvm-svn: 237634
* MC: Clean up method names in MCContext.Jim Grosbach2015-05-184-17/+17
| | | | | | | The naming was a mish-mash of old and new style. Update to be consistent with the new. NFC. llvm-svn: 237594
* [mips][microMIPSr6] Implement ALIGN and AUI instructionsJozef Kolek2015-05-183-4/+59
| | | | | | | | This patch implements ALIGN and AUI instructions using mapping. Differential Revision: http://reviews.llvm.org/D8782 llvm-svn: 237563
* Remove MCAssembler.h include from MCStreamer.h and fix users of MCStreamer.hPete Cooper2015-05-151-0/+1
| | | | llvm-svn: 237483
* Remove 3 includes from MCInstrDesc.h and explicitly include them where neededPete Cooper2015-05-151-0/+1
| | | | llvm-svn: 237481
* MC: MCCodeGenInfo naming update. NFC.Jim Grosbach2015-05-151-1/+1
| | | | | | s/InitMCCodeGenInfo/initMCCodeGenInfo/ llvm-svn: 237471
* MC: Update MCCodeEmitter naming. NFC.Jim Grosbach2015-05-152-4/+4
| | | | | | s/EncodeInstruction/encodeInstruction/ llvm-svn: 237469
* MC: Update MCFixup naming. NFC.Jim Grosbach2015-05-151-12/+12
| | | | | | s/MCFixup::Create/MCFixup::create/ llvm-svn: 237468
* [mips] [IAS] Fix expansion of negative 32-bit immediates for LI/DLI.Toma Tabacu2015-05-151-5/+18
| | | | | | | | | | | | | | | | | | Summary: To maintain compatibility with GAS, we need to stop treating negative 32-bit immediates as 64-bit values when expanding LI/DLI. This currently happens because of sign extension. To do this we need to choose the 32-bit value expansion for values which use their upper 33 bits only for sign extension (i.e. no 0's, only 1's). Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8662 llvm-svn: 237428
* [mips] [IAS] Enforce .set nomacro.Toma Tabacu2015-05-141-0/+10
| | | | | | | | | | | | | | Summary: When used, ".set nomacro" causes warning messages to be reported when we expand pseudo-instructions to multiple machine instructions. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9564 llvm-svn: 237366
* [mips] [IAS] Emit .set macro/nomacro.Toma Tabacu2015-05-141-0/+2
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9563 llvm-svn: 237363
* [mips] Do not place users of $ra in the delay slot of call instructions.Vasileios Kalintiris2015-05-141-0/+8
| | | | | | | | | | | | | | | Summary: When we are trying to fill the delay slot of a call instruction, we must avoid filler instructions that use the $ra register. This fixes the test MultiSource/Applications/JM/lencod when we enable the forward delay slot filler. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9670 llvm-svn: 237362
* [mips] [IAS] Warn when LA is used with a 64-bit symbol.Toma Tabacu2015-05-141-8/+11
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9295 llvm-svn: 237356
* [mips] [IAS] Give expandLoadAddressSym() more specific arguments. NFC.Toma Tabacu2015-05-141-23/+13
| | | | | | | | | | | | | | | | Summary: If we only pass the necessary operands, we don't have to determine the position of the symbol operand when entering expandLoadAddressSym(). This simplifies the expandLoadAddressSym() code. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9291 llvm-svn: 237355
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-136-274/+274
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* [mips] [IAS] Preemptively fix warning introduced by r237255. NFC.Toma Tabacu2015-05-131-3/+6
| | | | | | | | | | | Some compilers warn about using the ternary operator with an unsigned variable and enum. I haven't seen this trigger in the llvm.org buildbots yet, but it probably will at some point. Reported by Daniel Sanders. llvm-svn: 237262
* [mips][microMIPSr6] Implement CLO and CLZ instructionsJozef Kolek2015-05-133-3/+45
| | | | | | | | This patch implements CLO and CLZ instructions using mapping. Differential Revision: http://reviews.llvm.org/D8553 llvm-svn: 237257
* [mips] [IAS] Unify common functionality of LA and LI.Toma Tabacu2015-05-131-86/+82
| | | | | | | | | | | | | | Summary: A side-effect of this is that LA gains proper handling of unsigned and positive signed 16-bit immediates and more accurate error messages. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9290 llvm-svn: 237255
* Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-05-134-68/+64
| | | | | | | The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-134-64/+68
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* [mips][microMIPSr6] Implement SELEQZ and SELNEZ instructionsJozef Kolek2015-05-123-3/+36
| | | | | | | | This patch implements SELEQZ and SELNEZ instructions using mapping. Differential Revision: http://reviews.llvm.org/D8497 llvm-svn: 237158
* [Mips] Return false for isFPCloseToIncomingSP()Petar Jovanovic2015-05-121-0/+2
| | | | | | | | | | | | | On Mips, frame pointer points to the same side of the frame as the stack pointer. This function is used to decide where to put register scavenging spill slot. So far, it was put on the wrong side of the frame, and thus it was too far away from $fp when frame was larger than 2^15 bytes. Patch by Vladimir Radosavljevic. http://reviews.llvm.org/D8895 llvm-svn: 237153
* [mips][FastISel] Handle calls with non legal types i8 and i16.Vasileios Kalintiris2015-05-121-1/+3
| | | | | | | | | | | | | | | | | | Summary: Allow calls with non legal integer types based on i8 and i16 to be processed by mips fast-isel. Based on a patch by Reed Kotler. Test Plan: "Make check" test forthcoming. Test-suite passes at O0/O2 and with mips32 r1/r2 Reviewers: rkotler, dsanders Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D6770 llvm-svn: 237121
* [mips][FastISel] Allow computation of addresses from constant expressions.Vasileios Kalintiris2015-05-121-2/+4
| | | | | | | | | | | | | | | | | | | Summary: Try to compute addresses when the offset from a memory location is a constant expression. Based on a patch by Reed Kotler. Test Plan: Passes test-suite for -O0/O2 and mips 32 r1/r2 Reviewers: rkotler, dsanders Subscribers: llvm-commits, aemerson, rfuhler Differential Revision: http://reviews.llvm.org/D6767 llvm-svn: 237117
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