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* Don't modify MO while use_iterator is still pointing to it.Jakob Stoklund Olesen2012-08-091-3/+4
| | | | llvm-svn: 161626
* Another 32 to 64 bit sign extension bug.Jack Carter2012-08-091-1/+1
| | | | | | The fields in the td definition were switched. llvm-svn: 161607
* The define for 64 bit sign extension neglected to Jack Carter2012-08-071-7/+8
| | | | | | | | | | | | | | | | | | | | initialize fields of the class that it used. The result was nonsense code. Before: 0000000000000000 <foo>: 0: 00441100 0x441100 4: 03e00008 jr ra 8: 00000000 nop After: 0000000000000000 <foo>: 0: 00041000 sll v0,a0,0x0 4: 03e00008 jr ra 8: 00000000 nop llvm-svn: 161377
* Mips relocation R_MIPS_64 relocates a 64 bit double word.Jack Carter2012-08-072-0/+4
| | | | | | | | I hit this in a very large program (spirit.cpp), but have not figured out how to make a small make check test for it. llvm-svn: 161366
* The Mips64InstrInfo.td definitions DynAlloc64 LEA_ADDiu64 Jack Carter2012-08-062-14/+10
| | | | | | | | | | were using a class defined for 32 bit instructions and thus the instruction was for addiu instead of daddiu. This was corrected by adding the instruction opcode as a field in the base class to be filled in by the defs. llvm-svn: 161359
* Mips relocations R_MIPS_HIGHER and R_MIPS_HIGHEST.Jack Carter2012-08-064-2/+30
| | | | | | | | | | | | | | These 2 relocations gain access to the highest and the second highest 16 bits of a 64 bit object. R_MIPS_HIGHER %higher(A+S) The %higher(x) function is [ (((long long) x + 0x80008000LL) >> 32) & 0xffff ]. R_MIPS_HIGHEST %highest(A+S) The %highest(x) function is [ (((long long) x + 0x800080008000LL) >> 48) & 0xffff ]. llvm-svn: 161348
* 1. Redo mips16 instructions to avoid multiple opcodes for same instruction.Akira Hatanaka2012-08-032-54/+269
| | | | | | | | | Change these to patterns. 2. Add another 16 instructions. Patch by Reed Kotler. llvm-svn: 161272
* Move the code that creates instances of MipsInstrInfo and MipsFrameLowering outAkira Hatanaka2012-08-029-29/+51
| | | | | | of MipsTargetMachine.cpp. llvm-svn: 161191
* Set transient stack alignment in constructor of MipsFrameLowering and re-enableAkira Hatanaka2012-08-021-3/+2
| | | | | | test o32_cc_vararg.ll. llvm-svn: 161189
* Implement MipsJITInfo::replaceMachineCodeForFunction.Akira Hatanaka2012-08-011-1/+46
| | | | | | | | | | No new test case is added. This patch makes test JITTest.FunctionIsRecompiledAndRelinked pass on mips platform. Patch by Petar Jovanovic. llvm-svn: 161098
* Remove unused variable.Akira Hatanaka2012-08-011-1/+0
| | | | llvm-svn: 161095
* Implement MipsSERegisterInfo::eliminateCallFramePseudoInstr. The function emitsAkira Hatanaka2012-07-319-41/+71
| | | | | | | instructions that decrement and increment the stack pointer before and after a call when the function does not have a reserved call frame. llvm-svn: 161093
* Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo andAkira Hatanaka2012-07-3113-72/+268
| | | | | | MipsSERegisterInfo. llvm-svn: 161092
* Add definitions of two subclasses of MipsFrameLowering, Mips16FrameLowering andAkira Hatanaka2012-07-319-219/+415
| | | | | | | | | | MipsSEFrameLowering. Implement MipsSEFrameLowering::hasReservedCallFrame. Call frames will not be reserved if there is a call with a large call frame or there are variable sized objects on the stack. llvm-svn: 161090
* Add Mips16InstrInfo.cpp and MipsSEInstrInfo.cpp to CMakeLists.txt.Akira Hatanaka2012-07-311-0/+2
| | | | llvm-svn: 161083
* Add definitions of two subclasses of MipsInstrInfo, MipsInstrInfo (for mips16),Akira Hatanaka2012-07-319-361/+624
| | | | | | and MipsSEInstrInfo (for mips32/64). llvm-svn: 161081
* Delete mips64 target machine classes. mips target machines can be used in placeAkira Hatanaka2012-07-312-88/+46
| | | | | | of them. llvm-svn: 161080
* Let PEI::calculateFrameObjectOffsets compute the final stack size rather thanAkira Hatanaka2012-07-312-12/+1
| | | | | | computing it in MipsFrameLowering::emitPrologue. llvm-svn: 161078
* Expand DYNAMIC_STACKALLOC nodes rather than doing custom-lowering.Akira Hatanaka2012-07-314-66/+6
| | | | | | | The frame object which points to the dynamically allocated area will not be needed after changes are made to cease reserving call frames. llvm-svn: 161076
* Define ADJCALLSTACKDOWN/UP nodes. These nodes are emitted regardless of whetherAkira Hatanaka2012-07-314-38/+33
| | | | | | | or not it is in mips16 mode. Define MipsPseudo (mode-independant pseudo) and PseudoSE (mips32/64 pseudo) classes. llvm-svn: 161071
* Change name of class MipsInst to InstSE to distinguish it from mips16'sAkira Hatanaka2012-07-312-16/+16
| | | | | | instruction class. SE stands for standard encoding. llvm-svn: 161069
* When store nodes or memcpy nodes are created to copy the function callAkira Hatanaka2012-07-312-48/+32
| | | | | | | arguments to the stack in MipsISelLowering::LowerCall, use stack pointer and integer offset operands rather than frame object operands. llvm-svn: 161068
* Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined asAkira Hatanaka2012-07-313-38/+17
| | | | | | | | | single-precision load and store. Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect to map unaligned floating point load/store nodes to these instructions. llvm-svn: 161063
* Pass the correct call frame size to callseq_start node. This is needed toAkira Hatanaka2012-07-261-15/+10
| | | | | | | replace uses of function getMaxCallFrameSize defined in MipsFunctionInfo with the one MachineFrameInfo has. llvm-svn: 160841
* Fix call setup for PIC.Akira Hatanaka2012-07-262-6/+40
| | | | | | Patch by Reed Kotler. llvm-svn: 160774
* Eliminate the stack slot used to save the global base register.Akira Hatanaka2012-07-254-59/+15
| | | | | | | | The long branch pass (fixed in r160601) no longer uses the global base register to compute addresses of branch destinations, so it is not necessary to reserve a slot on the stack. llvm-svn: 160703
* Fix function MipsCodeEmitter::emitExternalSymbolAddress to pass testAkira Hatanaka2012-07-241-1/+1
| | | | | | | | ExecutionEngine/test-fp.ll. Patch by Petar Jovanovic. llvm-svn: 160653
* Add basic ability to setup call frame, and make procedure calls.Akira Hatanaka2012-07-238-44/+287
| | | | | | | | Hello world will compile and execute with this patch. Patch by Reed Kotler. llvm-svn: 160651
* Add comment for relocations MO_HIGHER and HIGHEST in MipsBaseInfo.h.Akira Hatanaka2012-07-231-0/+2
| | | | llvm-svn: 160636
* Fix Mips long branch pass.Akira Hatanaka2012-07-212-131/+136
| | | | | | | This pass no longer requires that the global pointer value be saved to the stack or register since it uses bal instruction to compute branch distance. llvm-svn: 160601
* Add HIGHER and HIGHEST relocations to Mips backend.Akira Hatanaka2012-07-213-1/+8
| | | | llvm-svn: 160599
* Revert accidental commit.Akira Hatanaka2012-07-218-288/+45
| | | | llvm-svn: 160598
* Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind.Akira Hatanaka2012-07-218-45/+288
| | | | | | Test case will be added later when long branch patch is checked in. llvm-svn: 160597
* Mips specific inline asm operand modifier 'M':Jack Carter2012-07-181-3/+8
| | | | | | | | | | | | | | | | | | | | | | Print the high order register of a double word register operand. In 32 bit mode, a 64 bit double word integer will be represented by 2 32 bit registers. This modifier causes the high order register to be used in the asm expression. It is useful if you are using doubles in assembler and continue to control register to variable relationships. This patch also fixes a related bug in a previous patch: case 'D': // Second part of a double word register operand case 'L': // Low order register of a double word register operand case 'M': // High order register of a double word register operand I got 'D' and 'M' confused. The second part of a double word operand will only match 'M' for one of the endianesses. I had 'L' and 'D' be the opposite twins when 'L' and 'M' are. llvm-svn: 160429
* Clean up Mips16InstrFormats.td and Mips16InstrInfo.td.Akira Hatanaka2012-07-172-93/+117
| | | | | | Patch by Reed Kotler. llvm-svn: 160403
* Doubleword Shift Left Logical Plus 32Jack Carter2012-07-164-1/+57
| | | | | | | | | | | | | | | | | | | | | Mips shift instructions DSLL, DSRL and DSRA are transformed into DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between 32 and 63 Here is a description of DSLL: Purpose: Doubleword Shift Left Logical Plus 32 To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits Description: GPR[rd] <- GPR[rt] << (sa+32) The 64-bit doubleword contents of GPR rt are shifted left, inserting zeros into the emptied bits; the result is placed in GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa. This patch implements the direct object output of these instructions. llvm-svn: 160277
* Remove variable_ops from call instructions in most targets.Jakob Stoklund Olesen2012-07-132-4/+4
| | | | | | | | Call instructions are no longer required to be variadic, and variable_ops should only be used for instructions that encode a variable number of arguments, like the ARM stm/ldm instructions. llvm-svn: 160189
* The Mips specific relocation R_MIPS_GOT_DISP Jack Carter2012-07-134-4/+12
| | | | | | | | | | is used in cases where global symbols are directly represented in the GOT and we use an offset into the global offset table. This patch adds direct object support for R_MIPS_GOT_DISP. llvm-svn: 160183
* Patch for Mips direct object generation.Jack Carter2012-07-111-0/+8
| | | | | | | | | | | | | | | | | When WriteFragmentData() case FT_align called Asm.getBackend().writeNopData() is called, nothing is done since Mips implementation of writeNopData just returned "true". For some reason this has not caused problems in 32 bit mode, but in 64 bit mode it caused an assert when processing multiple function units. The test case included will assert without this patch. It runs twice with different flags to prevent false positives due to changes in code generation over time. llvm-svn: 160084
* This change removes an "initialization" warning.Jack Carter2012-07-111-4/+3
| | | | | | | | Even though variable in question could not be initialized before use, the code was such that the compiler had no way of knowing that. llvm-svn: 160081
* In register classes in MipsRegisterInfo.td, list the registers in ascendingAkira Hatanaka2012-07-111-99/+114
| | | | | | | | order of binary encoding. Patch by Vladimir Medic. llvm-svn: 160073
* Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC.Akira Hatanaka2012-07-112-3/+17
| | | | llvm-svn: 160064
* Lower RETURNADDR node in Mips backend.Akira Hatanaka2012-07-113-5/+31
| | | | | | Patch by Sasa Stankovic. llvm-svn: 160031
* Mips specific inline asm operand modifier 'L'.Jack Carter2012-07-101-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Low order register of a double word register operand. Operands are defined by the name of the variable they are marked with in the inline assembler code. This is a way to specify that the operand just refers to the low order register for that variable. It is the opposite of modifier 'D' which specifies the high order register. Example: main() { long long ll_input = 0x1111222233334444LL; long long ll_val = 3; int i_result = 0; __asm__ __volatile__( "or %0, %L1, %2" : "=r" (i_result) : "r" (ll_input), "r" (ll_val)); } Which results in: lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -8 addu $2, $2, $25 sw $2, 0($sp) lui $2, 13107 ori $3, $2, 17476 <-- Low 32 bits of ll_input lui $2, 4369 ori $4, $2, 8738 <-- High 32 bits of ll_input addiu $5, $zero, 3 <-- Low 32 bits of ll_val addiu $2, $zero, 0 <-- High 32 bits of ll_val #APP or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val #NO_APP addiu $sp, $sp, 8 jr $ra If not direction is done for the long long for 32 bit variables results in using the low 32 bits as ll_val shows. There is an existing bug if 'L' or 'D' is used for the destination register for 32 bit long longs in that the target value will be updated incorrectly for the non-specified part unless explicitly set within the inline asm code. llvm-svn: 160028
* Make register Mips::RA allocatable if not in mips16 mode.Akira Hatanaka2012-07-109-37/+88
| | | | llvm-svn: 159971
* Reapply r158846.Akira Hatanaka2012-07-091-114/+77
| | | | | | | Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
* revert r159851.Akira Hatanaka2012-07-062-131/+166
| | | | llvm-svn: 159854
* Reapply r158846.Akira Hatanaka2012-07-062-166/+131
| | | | | | Include file MipsGenRegisterInfo.inc. llvm-svn: 159851
* Changes per review of commit 159787Jack Carter2012-07-061-6/+5
| | | | | | | | | | Mips specific inline asm operand modifier D. Comment changes and predicate change. llvm-svn: 159802
* Mips specific inline asm operand modifier D.Jack Carter2012-07-051-7/+41
| | | | | | | | | | | | Print the second half of a double word operand. The include list was cleaned up a bit as well. Also the test case was modified to test for both big and little patterns. llvm-svn: 159787
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