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* Reapply 154038 without the failing test.Akira Hatanaka2012-04-041-3/+3
| | | | llvm-svn: 154062
* Revert r154038. It was causing make check failures.Owen Anderson2012-04-041-3/+3
| | | | llvm-svn: 154054
* Fix LowerGlobalAddress to produce instructions with the correct relocationAkira Hatanaka2012-04-041-3/+3
| | | | | | types for N32 ABI. Add new test case and update existing ones. llvm-svn: 154038
* Fix LowerJumpTable to produce instructions with the correct relocationAkira Hatanaka2012-04-041-2/+2
| | | | | | | types for N32 ABI. Test case will be updated after the patch that fixes TargetLowering::getPICJumpTableRelocBase is checked in. llvm-svn: 154036
* Fix LowerConstantPool to produce instructions with the correct relocationAkira Hatanaka2012-04-041-2/+2
| | | | | | types for N32 ABI and update test case. llvm-svn: 154034
* Fix LowerBlockAddress to produce instructions with the correct relocationAkira Hatanaka2012-04-041-2/+2
| | | | | | types for N32 ABI and update test case. llvm-svn: 154031
* Revert r153924. Delete test/MC/Disassembler/Mips and ↵Akira Hatanaka2012-04-034-0/+0
| | | | | | lib/Target/Mips/Disassembler. llvm-svn: 153926
* Revert r153924. There were buildbot failures.Akira Hatanaka2012-04-0313-925/+104
| | | | llvm-svn: 153925
* MIPS disassembler support.Akira Hatanaka2012-04-0313-104/+925
| | | | | | Patch by Vladimir Medic. llvm-svn: 153924
* Initial 64 bit direct object support.Akira Hatanaka2012-04-024-23/+49
| | | | | | | | | | | This patch allows llvm to recognize that a 64 bit object file is being produced and that the subsequently generated ELF header has the correct information. The test case checks for both big and little endian flavors. Patch by Jack Carter. llvm-svn: 153889
* Move getOpcodeName from the various target InstPrinters into the superclass ↵Benjamin Kramer2012-04-022-5/+0
| | | | | | | | MCInstPrinter. All implementations used the same code. llvm-svn: 153866
* Remove getInstructionName from MCInstPrinter implementations in favor of ↵Craig Topper2012-04-022-3/+2
| | | | | | using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations. llvm-svn: 153863
* Make MCInstrInfo available to the MCInstPrinter. This will be used to remove ↵Craig Topper2012-04-022-3/+5
| | | | | | getInstructionName and the static data it contains since the same tables are already in MCInstrInfo. llvm-svn: 153860
* Select static relocation model if it is jitting.Akira Hatanaka2012-03-311-1/+3
| | | | llvm-svn: 153795
* Expand FREM.Akira Hatanaka2012-03-291-0/+2
| | | | llvm-svn: 153671
* Turn off post-RA scheduler by default.Akira Hatanaka2012-03-281-1/+1
| | | | llvm-svn: 153557
* Turn on post register allocation scheduler.Akira Hatanaka2012-03-284-0/+22
| | | | llvm-svn: 153554
* Sort relocation entries before they are written out to a file. MIPS ABIAkira Hatanaka2012-03-281-0/+103
| | | | | | | imposes a constraint that GOT16 referring to a local symbol or HI16 has to be followed immediately by a matching LO16 relocation. llvm-svn: 153553
* Emit all directives except for ".cprestore" during asm printing rather than emitAkira Hatanaka2012-03-287-151/+188
| | | | | | | | | | | | | | | | them as machine instructions. Directives ".set noat" and ".set at" are now emitted only at the beginning and end of a function except in the case where they are emitted to enclose .cpload with an immediate operand that doesn't fit in 16-bit field or unaligned load/stores. Also, make the following changes: - Remove function isUnalignedLoadStore and use a switch-case statement to determine whether an instruction is an unaligned load or store. - Define helper function CreateMCInst which generates an instance of an MCInst from an opcode and a list of operands. llvm-svn: 153552
* Mark flag neverHasSideEffects of pattern-less instructions that do not haveAkira Hatanaka2012-03-281-0/+5
| | | | | | any side effects. llvm-svn: 153551
* Remove trailing white space.Akira Hatanaka2012-03-271-1/+1
| | | | llvm-svn: 153536
* Add member EmitNOAT and its setter and getter functions to class ↵Akira Hatanaka2012-03-271-1/+6
| | | | | | | | | MipsFunctionInfo. If EmitNOAT is true, directives ".set noat" and ".set at" are emitted at the beginning and end of a function. llvm-svn: 153528
* Prune some includesCraig Topper2012-03-273-4/+1
| | | | llvm-svn: 153502
* Pass the llvm IR pointer value and offset to the constructor ofAkira Hatanaka2012-03-271-9/+13
| | | | | | | | | | | | MachinePointerInfo when getStore is called to create a node that stores an argument passed in register to the stack. Without this change, the post RA scheduler will fail to discover the dependencies between the stores instructions and the instructions that load from a structure passed by value. The link to the related discussion is here: http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-March/048055.html llvm-svn: 153499
* Fix bug in LowerConstantPool. Akira Hatanaka2012-03-271-1/+1
| | | | llvm-svn: 153498
* Add T9 to the list of live-in registers of the entry basic block. Akira Hatanaka2012-03-271-0/+2
| | | | llvm-svn: 153497
* Retrieve and add the offset of a symbol in applyFixup rather than retrieve andAkira Hatanaka2012-03-272-67/+67
| | | | | | | set it in MipsMCCodeEmitter::getMachineOpValue. Assert in getMachineOpValue if MachineOperand MO is of an unexpected type. llvm-svn: 153494
* Define function MipsGetSymAndOffset which returns a fixup's symbol and theAkira Hatanaka2012-03-271-0/+30
| | | | | | offset applied to it. llvm-svn: 153493
* Rewrite computation of Value in adjustFixupValue so that the upper 48-bits areAkira Hatanaka2012-03-271-1/+1
| | | | | | cleared. No functionality change. llvm-svn: 153491
* Reserve hardware registers.Akira Hatanaka2012-03-271-0/+4
| | | | llvm-svn: 153486
* Prune some includes and forward declarations.Craig Topper2012-03-261-7/+1
| | | | llvm-svn: 153429
* Add typecast to silence -Wswitch warning introduced by r153153.Craig Topper2012-03-211-1/+1
| | | | llvm-svn: 153155
* Incremental big endian patch by Jack Carter.Akira Hatanaka2012-03-212-13/+30
| | | | | | | | These changes allow us to compile big endian from the command line for 32 bit Mips targets. This patch will result in code and data actually being produced in the correct endianess. llvm-svn: 153153
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-1713-20/+16
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* Convert more static tables of registers used by calling convention to ↵Craig Topper2012-03-111-10/+10
| | | | | | uint16_t to reduce space. llvm-svn: 152538
* Use uint16_t to store registers and opcode in static tables in the target ↵Craig Topper2012-03-111-2/+2
| | | | | | specific backends. llvm-svn: 152537
* Do not custom lower i64 nodes if i64 is not a legal type. Move lines that setAkira Hatanaka2012-03-101-11/+14
| | | | | | operation action of nodes. llvm-svn: 152452
* Lower SETCC nodes during legalization. Previously, it was lowered in DAG ↵Akira Hatanaka2012-03-092-20/+16
| | | | | | combine pass. llvm-svn: 152450
* Remove unused header files.Akira Hatanaka2012-03-091-2/+0
| | | | llvm-svn: 152447
* Fix undefined behavior in the Mips backend.Ahmed Charles2012-03-092-15/+15
| | | | llvm-svn: 152390
* Invoke setTargetDAGCombine for SELECT.Akira Hatanaka2012-03-081-0/+1
| | | | llvm-svn: 152290
* Swap the operands of a select node if the false (the second) operand is 0.Akira Hatanaka2012-03-081-0/+35
| | | | | | | | | | | | For example, this pattern (select (setcc lhs, rhs, cc), true, 0) is transformed to this one: (select (setcc lhs, rhs, inverse(cc)), 0, true) This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to replace 0 with $zero. llvm-svn: 152285
* Set minimum function alignment to 3 if target is Mips64.Akira Hatanaka2012-03-081-1/+1
| | | | llvm-svn: 152282
* This patch eliminates redundant instructions that produce 0.Akira Hatanaka2012-03-081-1/+50
| | | | | | | | | | | | For example, the first instruction in the code below can be eliminated if the use of $vr0 is replaced with $zero: addiu $vr0, $zero, 0 add $vr2, $vr1, $vr0 add $vr2, $vr1, $zero llvm-svn: 152280
* Make MCRegisterInfo available to the the MCInstPrinter.Jim Grosbach2012-03-052-2/+4
| | | | | | | Used to allow context sensitive printing of super-register or sub-register references. llvm-svn: 152043
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-052-3/+3
| | | | | | static data size. llvm-svn: 152016
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-1/+1
| | | | llvm-svn: 152001
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-042-2/+2
| | | | | | size of static data. llvm-svn: 151996
* Changes for migrating to using register mask operands.Akira Hatanaka2012-03-016-48/+45
| | | | llvm-svn: 151847
* Fix bugs which were introduced when support for base+index floating point loadsAkira Hatanaka2012-03-014-10/+35
| | | | | | | | | | | and stores was added. - SelectAddr should return false if Parent is an unaligned f32 load or store. - Only aligned load and store nodes should be matched to select reg+imm floating point instructions. - MIPS does not have support for f64 unaligned load or store instructions. llvm-svn: 151843
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