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* [mips] synci microMIPS instruction definition.Simon Dardis2016-10-243-3/+15
| | | | | | | | | | | | | Add synci to the microMIPS instruction definitions, mark the MIPS sync & synci as not being part of microMIPS. This does not cover the sync instruction alias, as that will be handled with a different patch. Add sync to the valid tests for microMIPS. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D25795 llvm-svn: 284962
* [mips][ias] Handle more complicated expressions for memory operandsSimon Dardis2016-10-181-2/+54
| | | | | | | | | | | | | | | | This patch teaches ias for mips to handle expressions such as (8*4)+(8*31)($sp). Such expression typically occur from the expansion of multiple macro definitions. This partially resolves PR/30383. Thanks to Sean Bruno for reporting the issue! Reviewers: zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D24667 llvm-svn: 284485
* [mips] Fix sync instruction definitionSimon Dardis2016-10-182-2/+8
| | | | | | | | | | | | | | | | | | | | | | | The 'sync' instruction for MIPS was defined in MIPS-II as taking no operands. MIPS32 extended the define of 'sync' as taking an optional unsigned 5 bit immediate. This patch correct the definition of sync so that it is accepted with an operand of 0 or no operand for MIPS-II to MIPS-V, and a 5 bit unsigned immediate for MIPS32 and later revisions. Additionally a clear error is given when the MIPS32 version of sync is used when targeting pre MIPS32. This partially resolves PR/30714. Thanks to Daniel Sanders for reporting this issue! Reveiwers: vkalintiris Differential Revision: https://reviews.llvm.org/D25672 llvm-svn: 284483
* [mips] Macro expansion for ld, sd for O32Simon Dardis2016-10-182-0/+106
| | | | | | | | | | | | | | | | | | | | | | ld and sd when assembled for the O32 ABI expand to a pair of 32 bit word loads or stores using the specified source or destination register and the next register. This patch does not add support for the cases where the offset is greater than a 16 bit signed immediate as that would lead to a wrong/misleading error message as the assembler would report "instruction requires a CPU feature not currently enabled" for ld & sd for MIPS64 when their offset is not a signed 16 bit number. This fixes PR/29159. Thanks to Sean Bruno for reporting this issue! Reviewers: vkalintiris, seanbruno, zoran.jovanovic Differential Review: https://reviews.llvm.org/D24556 llvm-svn: 284481
* [mips][FastISel] Instantiate the MipsFastISel class only for targets that ↵Vasileios Kalintiris2016-10-182-22/+13
| | | | | | | | | | | | | | | | | | support FastISel. Summary: Instead of instantiating the MipsFastISel class and checking if the target is supported in the overriden methods, we should perform that check before creating the class. This allows us to enable FastISel *only* for targets that truly support it, ie. MIPS32 to MIPS32R5. Reviewers: sdardis Subscribers: ehostunreach, llvm-commits Differential Revision: https://reviews.llvm.org/D24824 llvm-svn: 284475
* [mips] Fix aui/daui/dahi/dati for MIPSR6Simon Dardis2016-10-147-17/+52
| | | | | | | | | | | | For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 284218
* [mips] Add IAS support for dvp, evpSimon Dardis2016-10-134-4/+44
| | | | | | | | | | | | | These instructions were only defined for microMIPSR6 previously. Add definitions for MIPSR6, correct definitions for microMIPSR6, flag these instructions as having unmodelled side effects (they disable/enable virtual processors) and add missing disassember tests for microMIPSR6. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24291 llvm-svn: 284115
* Revert r283690, "MC: Remove unused entities."Peter Collingbourne2016-10-101-1/+1
| | | | llvm-svn: 283814
* Move the global variables representing each Target behind accessor functionMehdi Amini2016-10-097-38/+56
| | | | | | | | This avoids "static initialization order fiasco" Differential Revision: https://reviews.llvm.org/D25412 llvm-svn: 283702
* MC: Remove unused entities.Peter Collingbourne2016-10-091-1/+1
| | | | llvm-svn: 283691
* Turn cl::values() (for enum) from a vararg function to using C++ variadic ↵Mehdi Amini2016-10-081-2/+1
| | | | | | | | | | | | | | | template The core of the change is supposed to be NFC, however it also fixes what I believe was an undefined behavior when calling: va_start(ValueArgs, Desc); with Desc being a StringRef. Differential Revision: https://reviews.llvm.org/D25342 llvm-svn: 283671
* Target: Remove unused patterns and transforms. NFC.Peter Collingbourne2016-10-073-13/+0
| | | | llvm-svn: 283515
* [mips][ias] fix li macro when values are negated with ~Simon Dardis2016-10-052-6/+34
| | | | | | | | | | | | | | | The integrated assembler evaluates the expressions such as ~0x80000000 to 0xffffffff7fffffff early in the parsing process. This patch adds compatibility with gas so that li loads the expected value (0x7fffffff) in those cases. This only occurs iff all the upper 32bits are set and maintains existing checks by not truncating the result down to 32 bits if any of the the upper bits are not set. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D23399 llvm-svn: 283353
* Recommit: "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-057-19/+43
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
* Revert "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-058-77/+25
| | | | | | | This reverts commit r282485 which contain two patches instead of one. llvm-svn: 283327
* [mips][fastisel] Consider soft-float an unsupported floating point modeSimon Dardis2016-10-041-2/+6
| | | | | | | | | | | Treat soft-float as unsupported for fast-isel. Additionally, ensure we check that lowering f32 arguments also considers the case of soft-float mode. Reviewers: ehostunreach, vkalintiris, zoran.jovanovic Differential Review: https://reviews.llvm.org/D24505 llvm-svn: 283209
* Use StringRef instead of raw pointers in MCAsmInfo/MCInstrInfo APIs (NFC)Mehdi Amini2016-10-011-2/+2
| | | | llvm-svn: 283018
* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-0110-22/+10
| | | | llvm-svn: 283004
* Remove an unnecessary duplicate initialization of TLOF from the MipsEric Christopher2016-09-291-4/+0
| | | | | | | | | | | AsmPrinter. This was reinitializing the Mangler after we moved the Mangler down to TLOF and causing us to have two different unnamed global values accessed with the same name. This should fix the problems on the ubsan tests here: http://lab.llvm.org:8011/builders/clang-cmake-mips/builds/15307 llvm-svn: 282675
* [mips] Disable tail calls temporarilySimon Dardis2016-09-271-1/+1
| | | | | | | | | | Disable tail calls while the remaining bugs are fixed. Enable only for tests. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24912 llvm-svn: 282487
* [mips] Add rsqrt, recip for MIPSSimon Dardis2016-09-278-25/+77
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 282485
* Add optimization bisect support to an optional Mips passAndrew Kaylor2016-09-261-0/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D19513 llvm-svn: 282428
* [mips] LLVM PR/30197 - Tail call incorrectly clobbers arguments for mipsSimon Dardis2016-09-211-1/+3
| | | | | | | | | | | | | | | | | The postRA scheduler performs alias analysis to determine if stores and loads can moved past each other. When a function has more arguments than argument registers for the calling convention used, excess arguments are spilled onto the stack. LLVM by default assumes that argument slots are immutable, unless the function contains a tail call. Without the knowledge of that a function contains a tail call site, stores and loads to fixed stack slots may be re-ordered causing the out-going arguments to clobber the incoming arguments before the incoming arguments are supposed to be dead. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24077 llvm-svn: 282063
* Defer asm errors to post-statement failureNirav Dave2016-09-161-40/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recommitting after fixing AsmParser initialization and X86 inline asm error cleanup. Allow errors to be deferred and emitted as part of clean up to simplify and shorten Assembly parser code. This will allow error messages to be emitted in helper functions and be modified by the caller which has better context. As part of this many minor cleanups to the Parser: * Unify parser cleanup on error * Add Workaround for incorrect return values in ParseDirective instances * Tighten checks on error-signifying return values for parser functions and fix in-tree TargetParsers to be more consistent with the changes. * Fix AArch64 test cases checking for spurious error messages that are now fixed. These changes should be backwards compatible with current Target Parsers so long as the error status are correctly returned in appropriate functions. Reviewers: rnk, majnemer Subscribers: aemerson, jyknight, llvm-commits Differential Revision: https://reviews.llvm.org/D24047 llvm-svn: 281762
* [mips] Fix previous revert r281726.Simon Dardis2016-09-161-36/+0
| | | | llvm-svn: 281729
* Revert "[mips] Fix aui/daui/dahi/dati for MIPSR6"Simon Dardis2016-09-167-39/+47
| | | | | | This reverts r281724. Still need dsanders to accept this. llvm-svn: 281726
* [mips] Fix aui/daui/dahi/dati for MIPSR6Simon Dardis2016-09-167-11/+75
| | | | | | | | | | | | For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: vkalintiris, dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 281724
* Move the Mangler from the AsmPrinter down to TLOF and clean up theEric Christopher2016-09-162-6/+3
| | | | | | TLOF API accordingly. llvm-svn: 281708
* [mips][ias] Enable IAS by default for N64 on Debian mips64el.Simon Dardis2016-09-151-0/+4
| | | | | | | | | | | | | | | | | | | Unfortunately we can't enable it for all N64 because it is not yet possible to distinguish N32 from N64. N64 has been confirmed to produce identical (within reason) objects to GAS during stage 2 of compiler recursion on N64-abit Fedora. Unfortunately, Fedora's triples do not distinguish N32 from N64 so I can't enable it by default there. I'm currently repeating this testing for Debian mips64el but it's very unlikely to produce a different result. Patch by: Daniel Sanders Reviewers: sdardis Differential Review: https://reviews.llvm.org/D22678 llvm-svn: 281607
* Finish renaming remaining analyzeBranch functionsMatt Arsenault2016-09-142-5/+5
| | | | llvm-svn: 281535
* Make analyzeBranch family of instruction names consistentMatt Arsenault2016-09-142-3/+3
| | | | | | | analyzeBranch was renamed to use lowercase first, rename the related set to match. llvm-svn: 281506
* AArch64: Use TTI branch functions in branch relaxationMatt Arsenault2016-09-142-4/+11
| | | | | | | | | The main change is to return the code size from InsertBranch/RemoveBranch. Patch mostly by Tim Northover llvm-svn: 281505
* getVectorElementType().getSizeInBits() -> getScalarSizeInBits() ; NFCISanjay Patel2016-09-141-2/+2
| | | | llvm-svn: 281495
* Revert r281336 (and r281337), it caused PR30372.Nico Weber2016-09-131-20/+40
| | | | llvm-svn: 281361
* Defer asm errors to post-statement failureNirav Dave2016-09-131-40/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recommitting after fixing AsmParser Initialization. Allow errors to be deferred and emitted as part of clean up to simplify and shorten Assembly parser code. This will allow error messages to be emitted in helper functions and be modified by the caller which has better context. As part of this many minor cleanups to the Parser: * Unify parser cleanup on error * Add Workaround for incorrect return values in ParseDirective instances * Tighten checks on error-signifying return values for parser functions and fix in-tree TargetParsers to be more consistent with the changes. * Fix AArch64 test cases checking for spurious error messages that are now fixed. These changes should be backwards compatible with current Target Parsers so long as the error status are correctly returned in appropriate functions. Reviewers: rnk, majnemer Subscribers: aemerson, jyknight, llvm-commits Differential Revision: https://reviews.llvm.org/D24047 llvm-svn: 281336
* Temporarily Revert "[MC] Defer asm errors to post-statement failure" as it's ↵Eric Christopher2016-09-131-20/+40
| | | | | | | | causing errors on the sanitizer bots. This reverts commit r281249. llvm-svn: 281280
* [MC] Defer asm errors to post-statement failureNirav Dave2016-09-121-40/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow errors to be deferred and emitted as part of clean up to simplify and shorten Assembly parser code. This will allow error messages to be emitted in helper functions and be modified by the caller which has better context. As part of this many minor cleanups to the Parser: * Unify parser cleanup on error * Add Workaround for incorrect return values in ParseDirective instances * Tighten checks on error-signifying return values for parser functions and fix in-tree TargetParsers to be more consistent with the changes. * Fix AArch64 test cases checking for spurious error messages that are now fixed. These changes should be backwards compatible with current Target Parsers so long as the error status are correctly returned in appropriate functions. Reviewers: rnk, majnemer Subscribers: aemerson, jyknight, llvm-commits Differential Revision: https://reviews.llvm.org/D24047 llvm-svn: 281249
* CodeGen: Give MachineBasicBlock::reverse_iterator a handle to the current MIDuncan P. N. Exon Smith2016-09-113-20/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that MachineBasicBlock::reverse_instr_iterator knows when it's at the end (since r281168 and r281170), implement MachineBasicBlock::reverse_iterator directly on top of an ilist::reverse_iterator by adding an IsReverse template parameter to MachineInstrBundleIterator. This replaces another hard-to-reason-about use of std::reverse_iterator on list iterators, matching the changes for ilist::reverse_iterator from r280032 (see the "out of scope" section at the end of that commit message). MachineBasicBlock::reverse_iterator now has a handle to the current node and has obvious invalidation semantics. r280032 has a more detailed explanation of how list-style reverse iterators (invalidated when the pointed-at node is deleted) are different from vector-style reverse iterators like std::reverse_iterator (invalidated on every operation). A great motivating example is this commit's changes to lib/CodeGen/DeadMachineInstructionElim.cpp. Note: If your out-of-tree backend deletes instructions while iterating on a MachineBasicBlock::reverse_iterator or converts between MachineBasicBlock::iterator and MachineBasicBlock::reverse_iterator, you'll need to update your code in similar ways to r280032. The following table might help: [Old] ==> [New] delete &*RI, RE = end() delete &*RI++ RI->erase(), RE = end() RI++->erase() reverse_iterator(I) std::prev(I).getReverse() reverse_iterator(I) ++I.getReverse() --reverse_iterator(I) I.getReverse() reverse_iterator(std::next(I)) I.getReverse() RI.base() std::prev(RI).getReverse() RI.base() ++RI.getReverse() --RI.base() RI.getReverse() std::next(RI).base() RI.getReverse() (For more details, have a look at r280032.) llvm-svn: 281172
* Revert "[mips] Fix c.<cc>.<fmt> instruction definition."Simon Dardis2016-09-0915-539/+209
| | | | | | | This reverts commit r281022. Mips buildbot broke, due to unhandled register class FCC. llvm-svn: 281033
* [mips] Fix c.<cc>.<fmt> instruction definition.Simon Dardis2016-09-0915-209/+539
| | | | | | | | | | | | | | | As part of this effort, remove MipsFCmp nodes and use tablegen patterns rather than custom lowering through C++. Unexpectedly, this improves codesize for microMIPS as previous floating point setcc expansions would materialize 0 and 1 into GPRs before using the relevant mov[tf].[sd] instruction. Now $zero is used directly. Reviewers: dsanders, vkalintiris, zoran.jovanovic Differential Review: https://reviews.llvm.org/D23118 llvm-svn: 281022
* [mips][microMIPS] Implement DBITSWAP, DLSA and LWUPC and add tests for AUI ↵Hrvoje Varga2016-09-088-12/+126
| | | | | | | | instructions Differential Revision: https://reviews.llvm.org/D16452 llvm-svn: 280909
* [mips] Disable the TImode shift libcalls for 32-bit targets.Vasileios Kalintiris2016-09-071-0/+7
| | | | | | | | | | | | | | Summary: The o32 ABI doesn't not support the TImode helpers. For the time being, disable just the shift libcalls as they break recursive builds on MIPS. Reviewers: sdardis Subscribers: llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D24259 llvm-svn: 280798
* [mips] Tighten FastISel restrictionsSimon Dardis2016-09-061-1/+17
| | | | | | | | | | | | | | | | | | LLVM PR/29052 highlighted that FastISel for MIPS attempted to lower arguments assuming that it was using the paired 32bit registers to perform operations for f64. This mode of operation is not supported for MIPSR6. This patch resolves the reported issue by adding additional checks for unsupported floating point unit configuration. Thanks to mike.k for reporting this issue! Reviewers: seanbruno, vkalintiris Differential Review: https://reviews.llvm.org/D23795 llvm-svn: 280706
* [mips] Include missed file from previous commitSimon Dardis2016-09-011-0/+1044
| | | | llvm-svn: 280377
* [mips] interAptiv based generic schedule modelSimon Dardis2016-09-013-3/+8
| | | | | | | | | | | This scheduler describes a processor which covers all MIPS ISAs based around the interAptiv and P5600 timings. Reviewers: vkalintiris, dsanders Differential Revision: https://reviews.llvm.org/D23551 llvm-svn: 280374
* Add ISD::EH_DWARF_CFA, simplify @llvm.eh.dwarf.cfa on Mips, fix on PowerPCHal Finkel2016-09-012-20/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LLVM has an @llvm.eh.dwarf.cfa intrinsic, used to lower the GCC-compatible __builtin_dwarf_cfa() builtin. As pointed out in PR26761, this is currently broken on PowerPC (and likely on ARM as well). Currently, @llvm.eh.dwarf.cfa is lowered using: ADD(FRAMEADDR, FRAME_TO_ARGS_OFFSET) where FRAME_TO_ARGS_OFFSET defaults to the constant zero. On x86, FRAME_TO_ARGS_OFFSET is lowered to 2*SlotSize. This setup, however, does not work for PowerPC. Because of the way that the stack layout works, the canonical frame address is not exactly (FRAMEADDR + FRAME_TO_ARGS_OFFSET) on PowerPC (there is a lower save-area offset as well), so it is not just a matter of implementing FRAME_TO_ARGS_OFFSET for PowerPC (unless we redefine its semantics -- We can do that, since it is currently used only for @llvm.eh.dwarf.cfa lowering, but the better to directly lower the CFA construct itself (since it can be easily represented as a fixed-offset FrameIndex)). Mips currently does this, but by using a custom lowering for ADD that specifically recognizes the (FRAMEADDR, FRAME_TO_ARGS_OFFSET) pattern. This change introduces a ISD::EH_DWARF_CFA node, which by default expands using the existing logic, but can be directly lowered by the target. Mips is updated to use this method (which simplifies its implementation, and I suspect makes it more robust), and updates PowerPC to do the same. Fixes PR26761. Differential Revision: https://reviews.llvm.org/D24038 llvm-svn: 280350
* MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, ↵Matthias Braun2016-08-254-4/+4
| | | | | | | | | | | | | compute it Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files. Differential Revision: http://reviews.llvm.org/D23850 llvm-svn: 279698
* [mips] Preparatory work for a generic schedulerSimon Dardis2016-08-248-360/+566
| | | | | | | | | | | | | Extend instruction definitions from nearly all ISAs to include appropriate instruction itineraries. Change MIPS16s gp prologue generation to use real instructions instead of using a pseudo instruction. Reviewers: dsanders, vkalintiris Differential Review: https://reviews.llvm.org/D23548 llvm-svn: 279623
* [mips][ias] Support .dtprel[d]word and .tprel[d]word directivesSimon Atanasyan2016-08-224-1/+113
| | | | | | | | | | | | | Assembler directives .dtprelword, .dtpreldword, .tprelword, and .tpreldword generates relocations R_MIPS_TLS_DTPREL32, R_MIPS_TLS_DTPREL64, R_MIPS_TLS_TPREL32, and R_MIPS_TLS_TPREL64 respectively. The main motivation for this patch is to be able to write test cases for checking correctness of the LLD linker's behaviour. Differential Revision: https://reviews.llvm.org/D23669 llvm-svn: 279439
* [mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix ↵Hrvoje Varga2016-08-227-96/+306
| | | | | | | | disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
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