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* Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not LegalDan Gohman2008-04-121-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | on any current target and aren't optimized in DAGCombiner. Instead of using intermediate nodes, expand the operations, choosing between simple loads/stores, target-specific code, and library calls, immediately. Previously, the code to emit optimized code for these operations was only used at initial SelectionDAG construction time; now it is used at all times. This fixes some cases where rep;movs was being used for small copies where simple loads/stores would be better. This also cleans up code that checks for alignments less than 4; let the targets make that decision instead of doing it in target-independent code. This allows x86 to use rep;movs in low-alignment cases. Also, this fixes a bug that resulted in the use of rep;stos for memsets of 0 with non-constant memory size when the alignment was at least 4. It's better to use the library in this case, which can be significantly faster when the size is large. This also preserves more SourceValue information when memory intrinsics are lowered into simple loads/stores. llvm-svn: 49572
* Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.Evan Cheng2008-03-312-13/+0
| | | | llvm-svn: 48995
* Fix "Control reaches the end of non-void function" warnings, Chris Lattner2008-03-302-0/+2
| | | | | | patch by David Chisnall. llvm-svn: 48963
* Add explicit keywords.Dan Gohman2008-03-251-1/+1
| | | | llvm-svn: 48801
* minor cleanupsChris Lattner2008-03-171-36/+30
| | | | llvm-svn: 48448
* Replace all target specific implicit def instructions with a target ↵Evan Cheng2008-03-151-5/+0
| | | | | | independent one: TargetInstrInfo::IMPLICIT_DEF. llvm-svn: 48380
* Use PassManagerBase instead of FunctionPassManager for functionsDan Gohman2008-03-113-7/+6
| | | | | | | | that merely add passes. This allows them to be used with either FunctionPassManager or PassManager, or even with a custom new kind of pass manager. llvm-svn: 48256
* Default ISD::PREFETCH to expand.Evan Cheng2008-03-101-1/+0
| | | | llvm-svn: 48169
* Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC'sScott Michel2008-03-102-1/+9
| | | | | | | | return ValueType can depend its operands' ValueType. This is a cosmetic change, no functionality impacted. llvm-svn: 48145
* Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} ↵Evan Cheng2008-03-081-0/+1
| | | | | | and prefetchnta instructions. llvm-svn: 48042
* Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to ↵Evan Cheng2008-02-281-1/+1
| | | | | | 16-byte boundaries. llvm-svn: 47703
* Final de-tabification.Bill Wendling2008-02-271-5/+5
| | | | llvm-svn: 47663
* Change "Name" to "AsmName" in the target register info. Gee, a refactoring toolBill Wendling2008-02-261-3/+3
| | | | | | would have been a Godsend here! llvm-svn: 47625
* I cannot find a libgcc function for this builtin. Therefor expanding it to ↵Andrew Lenharth2008-02-161-0/+1
| | | | | | a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support. llvm-svn: 47213
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-105-9/+9
| | | | llvm-svn: 46930
* It's not always safe to fold movsd into xorpd, etc. Check the alignment of ↵Evan Cheng2008-02-082-3/+6
| | | | | | the load address first to make sure it's 16 byte aligned. llvm-svn: 46893
* Dwarf requires variable entries to be in the source order. Right now, since ↵Evan Cheng2008-02-041-1/+0
| | | | | | we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead. llvm-svn: 46724
* Get rid of the annoying blank lines before labels.Evan Cheng2008-02-021-1/+0
| | | | llvm-svn: 46667
* SDIsel processes llvm.dbg.declare by recording the variable debug ↵Evan Cheng2008-02-021-0/+1
| | | | | | | | | information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes. For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time. llvm-svn: 46659
* Trivial patch to fix two warnings, please pull into llvm 2.2Chris Lattner2008-01-221-0/+3
| | | | llvm-svn: 46243
* This commit changes:Chris Lattner2008-01-172-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Legalize now always promotes truncstore of i1 to i8. 2. Remove patterns and gunk related to truncstore i1 from targets. 3. Rename the StoreXAction stuff to TruncStoreAction in TLI. 4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions. 5. Mark a wide variety of invalid truncstores as such in various targets, e.g. X86 currently doesn't support truncstore of any of its integer types. 6. Add legalize support for truncstores with invalid value input types. 7. Add a dag combine transform to turn store(truncate) into truncstore when safe. The later allows us to compile CodeGen/X86/storetrunc-fp.ll to: _foo: fldt 20(%esp) fldt 4(%esp) faddp %st(1) movl 36(%esp), %eax fstps (%eax) ret instead of: _foo: subl $4, %esp fldt 24(%esp) fldt 8(%esp) faddp %st(1) fstps (%esp) movl 40(%esp), %eax movss (%esp), %xmm0 movss %xmm0, (%eax) addl $4, %esp ret llvm-svn: 46140
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-072-8/+6
| | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
* Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptorChris Lattner2008-01-071-2/+2
| | | | llvm-svn: 45680
* Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflectsChris Lattner2008-01-072-2/+2
| | | | | | | | | | | | | | | that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. llvm-svn: 45674
* Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson2008-01-074-41/+42
| | | | | | Some day I'll get it all moved over... llvm-svn: 45672
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-1/+1
| | | | llvm-svn: 45667
* Change the 'isStore' inferrer to look for 'SDNPMayStore' Chris Lattner2008-01-061-1/+0
| | | | | | | | | | | instead of "ISD::STORE". This allows us to mark target-specific dag nodes as storing (such as ppc byteswap stores). This allows us to remove more explicit isStore flags from the .td files. Finally, add a warning for when a .td file contains an explicit isStore and tblgen is able to infer it. llvm-svn: 45654
* Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson2008-01-014-91/+84
| | | | llvm-svn: 45484
* Fix a problem where lib/Target/TargetInstrInfo.h would include and useChris Lattner2008-01-012-3/+2
| | | | | | | | | | a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. llvm-svn: 45475
* Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson2007-12-313-18/+21
| | | | | | Machine-level API cleanup instigated by Chris. llvm-svn: 45470
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-312-10/+9
| | | | | | | | | | | | | | that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
* Add new shorter predicates for testing machine operands for various types: Chris Lattner2007-12-303-13/+13
| | | | | | | | | | | | e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner2007-12-303-5/+5
| | | | | | Likewise setImmedValue -> setImm llvm-svn: 45453
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-2923-46/+46
| | | | llvm-svn: 45418
* remove attribution from lib Makefiles.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45415
* Setting GlobalDirective in TargetAsmInfo by default rather thanGordon Henriksen2007-12-231-1/+0
| | | | | | | providing a misleading facility. It's used once in the MIPS backend and hardcoded as "\t.globl\t" everywhere else. llvm-svn: 45338
* Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always ↵Evan Cheng2007-12-121-0/+1
| | | | | | re-materializable and they should not be spilled. llvm-svn: 44960
* Add a argument to storeRegToStackSlot and storeRegToAddr to specify whetherEvan Cheng2007-12-052-5/+6
| | | | | | the stored register is killed. llvm-svn: 44600
* Remove redundant foldMemoryOperand variants and other code clean up.Evan Cheng2007-12-022-16/+9
| | | | llvm-svn: 44517
* Allow some reloads to be folded in multi-use cases. Specifically testl r, r ↵Evan Cheng2007-12-012-7/+15
| | | | | | -> cmpl [mem], 0. llvm-svn: 44479
* Add parameter to getDwarfRegNum to permit targetsDale Johannesen2007-11-132-2/+2
| | | | | | | | to use different mappings for EH and debug info; no functional change yet. Fix warning in X86CodeEmitter. llvm-svn: 44056
* Unifacalize the CALLSEQ{START,END} stuff.Bill Wendling2007-11-131-5/+5
| | | | llvm-svn: 44045
* Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stackBill Wendling2007-11-132-13/+14
| | | | | | | | | | | adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If not, then there is the potential for the stack to be changed while the stack's being used by another instruction (like a call). This can only result in tears... llvm-svn: 44037
* Added JumpTable supportBruno Cardoso Lopes2007-11-126-34/+142
| | | | | | | Fixed some AsmPrinter issues Added GLOBAL_OFFSET_TABLE Node handle. llvm-svn: 44024
* Use TableGen to emit information for dwarf register numbers. Anton Korobeynikov2007-11-113-32/+40
| | | | | | | | This makes DwarfRegNum to accept list of numbers instead. Added three different "flavours", but only slightly tested on x86-32/linux. Please check another subtargets if possible, llvm-svn: 43997
* Better processor definitionBruno Cardoso Lopes2007-11-062-3/+5
| | | | llvm-svn: 43749
* Added support for PIC code with "explicit relocations" *only*.Bruno Cardoso Lopes2007-11-059-104/+215
| | | | | | | Removed all macro code for PIC (goodbye "la"). Support tested with shootout bench. llvm-svn: 43697
* Eliminate the remaining uses of getTypeSize. ThisDuncan Sands2007-11-051-2/+2
| | | | | | | | | | | | | | should only effect x86 when using long double. Now 12/16 bytes are output for long double globals (the exact amount depends on the alignment). This brings globals in line with the rest of LLVM: the space reserved for an object is now always the ABI size. One tricky point is that only 10 bytes should be output for long double if it is a field in a packed struct, which is the reason for the additional argument to EmitGlobalConstant. llvm-svn: 43688
* clo/clz aren't supported on mips I. Keep them around for when we'llEric Christopher2007-10-261-105/+107
| | | | | | want them later (mips32/64). llvm-svn: 43380
* - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but ↵Evan Cheng2007-10-182-4/+4
| | | | | | | | only returns the opcode of the instruction post unfolding. - Fix some copy+paste bugs. llvm-svn: 43153
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