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* [mips] Partially revert r193641. Stack alignment should not be determined byAkira Hatanaka2013-11-111-1/+1
| | | | | | | the floating point register mode. llvm-svn: 194423
* [mips] Compute stack alignment on the fly.Akira Hatanaka2013-10-301-3/+1
| | | | llvm-svn: 193673
* [mips] Align the stack to 16-bytes for mfp64.Akira Hatanaka2013-10-291-0/+5
| | | | llvm-svn: 193641
* Make first substantial checkin of my port of ARM constant islands code to Mips.Reed Kotler2013-10-271-0/+4
| | | | | | | | | | | | Before I just ported the shell of the pass. I've tried to keep everything nearly identical to the ARM version. I think it will be very easy to eventually merge these two and create a new more general pass that other targets can use. I have some improvements I would like to make to allow pools to be shared across functions and some other things. When I'm all done we can think about making a more general pass. More to be ported but the basic mechanism works now almost as good as gcc mips16. llvm-svn: 193509
* [mips] Do not generate INS/EXT nodes if target does not have support forAkira Hatanaka2013-10-091-0/+1
| | | | | | ins/ext. llvm-svn: 192330
* [mips] Define method MipsSubtarget::enableLongBranchPass.Akira Hatanaka2013-10-071-0/+4
| | | | llvm-svn: 192122
* Fix a problem with dual mips16/mips32 mode. When the underlying processorReed Kotler2013-08-301-0/+2
| | | | | | | | | | | | | has hard float, when you compile the mips32 code you have to make sure that it knows to compile any mips32 routines as hard float. I need to clean up the way mips16 hard float is specified but I need to first think through all the details. Mips16 always has a form of soft float, the difference being whether the underlying hardware has floating point. So it's not really necessary to pass the -soft-float to llvm since soft-float is always true for mips16 by virtue of the fact that it will not register floating point registers. By using this fact, I can simplify the way this is all handled. llvm-svn: 189690
* [mips] Add support for calling convention CC_MipsO32_FP64, which is used ↵Akira Hatanaka2013-08-201-0/+1
| | | | | | | | | | when the size of floating point registers is 64-bit. Test case will be added when support for mfhc1 and mthc1 is added. llvm-svn: 188847
* [Mips][msa] Added initial MSA support.Jack Carter2013-08-131-0/+4
| | | | | | | | | | | | * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
* [mips] Implement MipsTargetMachine::getInstrItineraryData().Akira Hatanaka2013-07-121-0/+1
| | | | llvm-svn: 186227
* Checkin in of first of several patches to finish implementation ofReed Kotler2013-05-101-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). llvm-svn: 181641
* This is for an experimental option -mips-os16. The idea is to compile allReed Kotler2013-04-101-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mips32 code as Mips16 unless it can't be compiled as Mips 16. For now this would happen as long as floating point instructions are not needed. Probably it would also make sense to compile as mips32 if atomic operations are needed too. There may be other cases too. A module pass prescans the IR and adds the mips16 or nomips16 attribute to functions depending on the functions needs. Mips 16 mode can result in a 40% code compression by utililizing 16 bit encoding of many instructions. The hope is for this to replace the traditional gcc way of dealing with Mips16 code using floating point which involves essentially using soft float but with a library implemented using mips32 floating point. This gcc method also requires creating stubs so that Mips32 code can interact with these Mips 16 functions that have floating point needs. My conjecture is that in reality this traditional gcc method would never win over this new method. I will be implementing the traditional gcc method also. Some of it is already done but I needed to do the stubs to finish the work and those required this mips16/32 mixed mode capability. I have more ideas for to make this new method much better and I think the old method will just live in llvm for anyone that needs the backward compatibility but I don't for what reason that would be needed. llvm-svn: 179185
* This patch enables llvm to switch between compiling for mips32/mips64 Reed Kotler2013-04-091-2/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and mips16 on a per function basis. Because this patch is somewhat involved I have provide an overview of the key pieces of it. The patch is written so as to not change the behavior of the non mixed mode. We have tested this a lot but it is something new to switch subtargets so we don't want any chance of regression in the mainline compiler until we have more confidence in this. Mips32/64 are very different from Mip16 as is the case of ARM vs Thumb1. For that reason there are derived versions of the register info, frame info, instruction info and instruction selection classes. Now we register three separate passes for instruction selection. One which is used to switch subtargets (MipsModuleISelDAGToDAG.cpp) and then one for each of the current subtargets (Mips16ISelDAGToDAG.cpp and MipsSEISelDAGToDAG.cpp). When the ModuleISel pass runs, it determines if there is a need to switch subtargets and if so, the owning pointers in MipsTargetMachine are appropriately changed. When 16Isel or SEIsel is run, they will return immediately without doing any work if the current subtarget mode does not apply to them. In addition, MipsAsmPrinter needs to be reset on a function basis. The pass BasicTargetTransformInfo is substituted with a null pass since the pass is immutable and really needs to be a function pass for it to be used with changing subtargets. This will be fixed in a follow on patch. llvm-svn: 179118
* [mips] Remove android calling convention.Akira Hatanaka2013-03-051-4/+0
| | | | | | | This calling convention was added just to handle functions which return vector of floats. The fix committed in r165585 solves the problem. llvm-svn: 176530
* This patch that sets the Mips ELF header flag for Jack Carter2013-02-051-0/+4
| | | | | | | | MicroMips architectures. Contributer: Zoran Jovanovic llvm-svn: 174360
* This patch implements runtime Mips specificJack Carter2013-01-301-0/+6
| | | | | | | | setting of ELF header e_flags. Contributer: Jack Carter llvm-svn: 173884
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-181-0/+7
| | | | | | | | | | | | | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Support for Mips register information sections. Mips ELF object files have a section that is dedicated to register use info. Some of this information such as the assumed Global Pointer value is used by the linker in relocation resolution. The register info file is .reginfo in o32 and .MIPS.options in 64 and n32 abi files. This patch contains the changes needed to create the sections, but leaves the actual register accounting for a future patch. Contributer: Jack Carter llvm-svn: 172847
* [mips] Delete unused sub-target features.Akira Hatanaka2012-12-071-9/+0
| | | | llvm-svn: 169578
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-041-1/+1
| | | | | | | | | | missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
* [mips] Add predicate HasFPIdx for floating-point indexed load instructionAkira Hatanaka2012-11-151-2/+4
| | | | | | support and use it in place of HasMips32r2Or64. llvm-svn: 168089
* Add flags and feature bits for mips dsp.Akira Hatanaka2012-09-211-0/+5
| | | | llvm-svn: 164428
* Add register Mips::GP to the list of reserved registers if target is bare-metalAkira Hatanaka2012-08-221-1/+5
| | | | | | | | to prevent it from being clobbered. mips uses $gp to access small data section. This bug was originally reported by Carl Norum. llvm-svn: 162340
* Add Android ABI to Mips backend to handle functions returning vectors of fourAkira Hatanaka2012-08-161-0/+4
| | | | | | floats. llvm-svn: 162008
* This patch adds a predicate to existing mips32 and mips64 so that thoseAkira Hatanaka2012-05-221-0/+2
| | | | | | | | | | | | | | | | | | | instruction encodings can be excluded during mips16 processing. This revision fixes the issue raised by Jim Grosbach. bool hasStandardEncoding() const { return !inMips16Mode(); } When micromips is added it will be bool StandardEncoding() const { return !inMips16Mode()&& !inMicroMipsMode(); } No additional testing is needed other than to assure that there is no regression from this patch. Patch by Reed Kotler. llvm-svn: 157234
* This patch adds the register class for MIPS16 as well as the ability forAkira Hatanaka2012-05-161-0/+4
| | | | | | | | | | | | | | | llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the mips16 ASE for mips32 by default. As part of fixing of adding this we discovered some small changes that need to be made to MipsInstrInfo::storeRegToStackSLot and MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead, per suggestion of Jakob Stoklund Olesen. Patch by Reed Kotler. llvm-svn: 156958
* Turn on post register allocation scheduler.Akira Hatanaka2012-03-281-0/+3
| | | | llvm-svn: 153554
* remove blanks, and some code formatJia Liu2012-02-281-1/+1
| | | | llvm-svn: 151625
* Add support for floating point base register + offset register addressing modeAkira Hatanaka2012-02-281-0/+2
| | | | | | load and store instructions. llvm-svn: 151611
* Unweaken vtables as per ↵David Blaikie2011-12-201-0/+1
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Set ABI if it hasn't been set on the command line.Akira Hatanaka2011-09-211-1/+1
| | | | | | Check if architecture & ABI combination is valid. llvm-svn: 140230
* Fix typo.Akira Hatanaka2011-09-211-2/+2
| | | | llvm-svn: 140229
* Change the names of functions isMips* to hasMips*.Akira Hatanaka2011-09-201-4/+4
| | | | llvm-svn: 140214
* Initial Mips64 support. Patch by Liu with some modifications.Akira Hatanaka2011-09-201-2/+7
| | | | llvm-svn: 140178
* Add comment.Akira Hatanaka2011-09-141-0/+1
| | | | llvm-svn: 139699
* O64 will not be supported.Akira Hatanaka2011-09-091-1/+1
| | | | llvm-svn: 139421
* Drop support for Mips1 and Mips2.Akira Hatanaka2011-09-091-2/+1
| | | | llvm-svn: 139405
* Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng2011-07-071-1/+2
| | | | llvm-svn: 134606
* Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.Evan Cheng2011-07-011-1/+1
| | | | llvm-svn: 134281
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-011-2/+2
| | | | llvm-svn: 134259
* - Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng2011-07-011-1/+4
| | | | | | | | | itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. llvm-svn: 134257
* Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-301-3/+3
| | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! llvm-svn: 134127
* Sink SubtargetFeature and TargetInstrItineraries (renamed ↵Evan Cheng2011-06-291-2/+1
| | | | | | MCInstrItineraries) into MC. llvm-svn: 134049
* Reverse unnecessary changes made in r129606 and r129608. There is no change ↵Akira Hatanaka2011-04-151-3/+3
| | | | | | in functionality. llvm-svn: 129612
* Fix lines that have incorrect indentation or exceed 80 columns. There is no ↵Akira Hatanaka2011-04-151-3/+3
| | | | | | change in functionality. llvm-svn: 129606
* Remove (hopefully) all trailing whitespaces from the mips backend. Patch by ↵Bruno Cardoso Lopes2011-03-041-8/+8
| | | | | | Hatanaka, Akira llvm-svn: 127003
* Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>Bruno Cardoso Lopes2010-11-121-2/+2
| | | | llvm-svn: 118864
* Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka ↵Bruno Cardoso Lopes2010-11-081-0/+2
| | | | | | (ahatanaka@mips.com) llvm-svn: 118447
* Fix a bunch of little errors that Clang complains about when its being pedanticDouglas Gregor2009-12-191-13/+13
| | | | llvm-svn: 91764
* reintroduce support for Mips "small" section handling. This is Chris Lattner2009-08-131-5/+0
| | | | | | | implemented somewhat differently than before, but it should have the same functionality and the previous testcase passes again. llvm-svn: 78900
* Restore some "small section" support code, reverting my patch from r76936.Chris Lattner2009-08-131-0/+5
| | | | llvm-svn: 78894
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