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path: root/llvm/lib/Target/Mips/MipsSubtarget.h
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* [mips] Remove android calling convention.Akira Hatanaka2013-03-051-4/+0
| | | | | | | This calling convention was added just to handle functions which return vector of floats. The fix committed in r165585 solves the problem. llvm-svn: 176530
* This patch that sets the Mips ELF header flag for Jack Carter2013-02-051-0/+4
| | | | | | | | MicroMips architectures. Contributer: Zoran Jovanovic llvm-svn: 174360
* This patch implements runtime Mips specificJack Carter2013-01-301-0/+6
| | | | | | | | setting of ELF header e_flags. Contributer: Jack Carter llvm-svn: 173884
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-181-0/+7
| | | | | | | | | | | | | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Support for Mips register information sections. Mips ELF object files have a section that is dedicated to register use info. Some of this information such as the assumed Global Pointer value is used by the linker in relocation resolution. The register info file is .reginfo in o32 and .MIPS.options in 64 and n32 abi files. This patch contains the changes needed to create the sections, but leaves the actual register accounting for a future patch. Contributer: Jack Carter llvm-svn: 172847
* [mips] Delete unused sub-target features.Akira Hatanaka2012-12-071-9/+0
| | | | llvm-svn: 169578
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-041-1/+1
| | | | | | | | | | missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
* [mips] Add predicate HasFPIdx for floating-point indexed load instructionAkira Hatanaka2012-11-151-2/+4
| | | | | | support and use it in place of HasMips32r2Or64. llvm-svn: 168089
* Add flags and feature bits for mips dsp.Akira Hatanaka2012-09-211-0/+5
| | | | llvm-svn: 164428
* Add register Mips::GP to the list of reserved registers if target is bare-metalAkira Hatanaka2012-08-221-1/+5
| | | | | | | | to prevent it from being clobbered. mips uses $gp to access small data section. This bug was originally reported by Carl Norum. llvm-svn: 162340
* Add Android ABI to Mips backend to handle functions returning vectors of fourAkira Hatanaka2012-08-161-0/+4
| | | | | | floats. llvm-svn: 162008
* This patch adds a predicate to existing mips32 and mips64 so that thoseAkira Hatanaka2012-05-221-0/+2
| | | | | | | | | | | | | | | | | | | instruction encodings can be excluded during mips16 processing. This revision fixes the issue raised by Jim Grosbach. bool hasStandardEncoding() const { return !inMips16Mode(); } When micromips is added it will be bool StandardEncoding() const { return !inMips16Mode()&& !inMicroMipsMode(); } No additional testing is needed other than to assure that there is no regression from this patch. Patch by Reed Kotler. llvm-svn: 157234
* This patch adds the register class for MIPS16 as well as the ability forAkira Hatanaka2012-05-161-0/+4
| | | | | | | | | | | | | | | llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the mips16 ASE for mips32 by default. As part of fixing of adding this we discovered some small changes that need to be made to MipsInstrInfo::storeRegToStackSLot and MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead, per suggestion of Jakob Stoklund Olesen. Patch by Reed Kotler. llvm-svn: 156958
* Turn on post register allocation scheduler.Akira Hatanaka2012-03-281-0/+3
| | | | llvm-svn: 153554
* remove blanks, and some code formatJia Liu2012-02-281-1/+1
| | | | llvm-svn: 151625
* Add support for floating point base register + offset register addressing modeAkira Hatanaka2012-02-281-0/+2
| | | | | | load and store instructions. llvm-svn: 151611
* Unweaken vtables as per ↵David Blaikie2011-12-201-0/+1
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Set ABI if it hasn't been set on the command line.Akira Hatanaka2011-09-211-1/+1
| | | | | | Check if architecture & ABI combination is valid. llvm-svn: 140230
* Fix typo.Akira Hatanaka2011-09-211-2/+2
| | | | llvm-svn: 140229
* Change the names of functions isMips* to hasMips*.Akira Hatanaka2011-09-201-4/+4
| | | | llvm-svn: 140214
* Initial Mips64 support. Patch by Liu with some modifications.Akira Hatanaka2011-09-201-2/+7
| | | | llvm-svn: 140178
* Add comment.Akira Hatanaka2011-09-141-0/+1
| | | | llvm-svn: 139699
* O64 will not be supported.Akira Hatanaka2011-09-091-1/+1
| | | | llvm-svn: 139421
* Drop support for Mips1 and Mips2.Akira Hatanaka2011-09-091-2/+1
| | | | llvm-svn: 139405
* Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng2011-07-071-1/+2
| | | | llvm-svn: 134606
* Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.Evan Cheng2011-07-011-1/+1
| | | | llvm-svn: 134281
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-011-2/+2
| | | | llvm-svn: 134259
* - Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng2011-07-011-1/+4
| | | | | | | | | itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. llvm-svn: 134257
* Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-301-3/+3
| | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! llvm-svn: 134127
* Sink SubtargetFeature and TargetInstrItineraries (renamed ↵Evan Cheng2011-06-291-2/+1
| | | | | | MCInstrItineraries) into MC. llvm-svn: 134049
* Reverse unnecessary changes made in r129606 and r129608. There is no change ↵Akira Hatanaka2011-04-151-3/+3
| | | | | | in functionality. llvm-svn: 129612
* Fix lines that have incorrect indentation or exceed 80 columns. There is no ↵Akira Hatanaka2011-04-151-3/+3
| | | | | | change in functionality. llvm-svn: 129606
* Remove (hopefully) all trailing whitespaces from the mips backend. Patch by ↵Bruno Cardoso Lopes2011-03-041-8/+8
| | | | | | Hatanaka, Akira llvm-svn: 127003
* Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>Bruno Cardoso Lopes2010-11-121-2/+2
| | | | llvm-svn: 118864
* Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka ↵Bruno Cardoso Lopes2010-11-081-0/+2
| | | | | | (ahatanaka@mips.com) llvm-svn: 118447
* Fix a bunch of little errors that Clang complains about when its being pedanticDouglas Gregor2009-12-191-13/+13
| | | | llvm-svn: 91764
* reintroduce support for Mips "small" section handling. This is Chris Lattner2009-08-131-5/+0
| | | | | | | implemented somewhat differently than before, but it should have the same functionality and the previous testcase passes again. llvm-svn: 78900
* Restore some "small section" support code, reverting my patch from r76936.Chris Lattner2009-08-131-0/+5
| | | | llvm-svn: 78894
* Remove -disable-mips-abicall and -enable-mips-absolute-call command-line Eli Friedman2009-08-031-11/+1
| | | | | | | | | | | | | options, which don't appear to be useful. -enable-mips-absolute-call is completely unused (and unless I'm mistaken, is supposed to have the same effect that -relocation-model=dynamic-no-pic should have), and -disable-mips-abicall appears to be effectively a synonym for -relocation-model=static. Adjust the few users of hasABICall to checks which seem more appropriate. Update MipsSubtarget, MipsTargetMachine, and MipselTargetMachine to synchronize with recent changes. llvm-svn: 77938
* Normalize Subtarget constructors to take a target triple string instead ofDaniel Dunbar2009-08-021-3/+2
| | | | | | | | | | Module*. Also, dropped uses of TargetMachine where unnecessary. The only target which still takes a TargetMachine& is Mips, I would appreciate it if someone would normalize this to match other targets. llvm-svn: 77918
* remove more remnants of small section support.Chris Lattner2009-07-241-5/+0
| | | | llvm-svn: 76936
* Added support for fround, fextend and FP_TO_SINTBruno Cardoso Lopes2009-05-271-1/+1
| | | | llvm-svn: 72483
* Propagate CPU string out of SubtargetFeaturesAnton Korobeynikov2009-05-231-1/+2
| | | | llvm-svn: 72335
* Added new features to represent specific instructions groupsBruno Cardoso Lopes2008-07-301-4/+28
| | | | llvm-svn: 54213
* Added initial support for small sections on Mips.Bruno Cardoso Lopes2008-07-211-0/+5
| | | | | | | Added gp_rel relocations to support addressing small section contents. Added command line to specify small section threshold in bytes. llvm-svn: 53869
* Added Subtarget support into RegisterInfoBruno Cardoso Lopes2008-07-141-4/+19
| | | | | | | | | | | | Added HasABICall and HasAbsoluteCall (equivalent to gcc -mabicall and -mno-shared). HasAbsoluteCall is not implemented but HasABICall is the default for o32 ABI. Now, both should help into a more accurate relocation types implementation. Added IsLinux is needed to choose between asm directives. Instruction name strings cleanup. AsmPrinter improved. llvm-svn: 53551
* Fixed features usage.Bruno Cardoso Lopes2008-07-091-7/+7
| | | | llvm-svn: 53277
* Fixe typos and 80 column size problemsBruno Cardoso Lopes2008-07-091-3/+3
| | | | llvm-svn: 53272
* Several changes to Mips backend, experimental fp support being the mostBruno Cardoso Lopes2008-07-051-5/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
* Some Mips minor fixesBruno Cardoso Lopes2008-06-041-2/+5
| | | | | | Added support for mips little endian arch => mipsel llvm-svn: 51923
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
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