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* This patch that sets the Mips ELF header flag for Jack Carter2013-02-051-1/+2
| | | | | | | | MicroMips architectures. Contributer: Zoran Jovanovic llvm-svn: 174360
* This patch implements runtime Mips specificJack Carter2013-01-301-2/+2
| | | | | | | | setting of ELF header e_flags. Contributer: Jack Carter llvm-svn: 173884
* [mips] Delete unused sub-target features.Akira Hatanaka2012-12-071-2/+2
| | | | llvm-svn: 169578
* [mips] Add predicate HasFPIdx for floating-point indexed load instructionAkira Hatanaka2012-11-151-2/+2
| | | | | | support and use it in place of HasMips32r2Or64. llvm-svn: 168089
* Initialize boolean variables in MipsSubtarget's constructor.Akira Hatanaka2012-09-251-1/+2
| | | | llvm-svn: 164642
* Add register Mips::GP to the list of reserved registers if target is bare-metalAkira Hatanaka2012-08-221-1/+5
| | | | | | | | to prevent it from being clobbered. mips uses $gp to access small data section. This bug was originally reported by Carl Norum. llvm-svn: 162340
* Fix coding style violations. Remove white spaces and tabs.Akira Hatanaka2012-06-141-2/+2
| | | | llvm-svn: 158471
* This patch adds the register class for MIPS16 as well as the ability forAkira Hatanaka2012-05-161-1/+1
| | | | | | | | | | | | | | | llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the mips16 ASE for mips32 by default. As part of fixing of adding this we discovered some small changes that need to be made to MipsInstrInfo::storeRegToStackSLot and MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead, per suggestion of Jakob Stoklund Olesen. Patch by Reed Kotler. llvm-svn: 156958
* Temporarily disable anti-dependence breaking for Mips until bug 12829 isAkira Hatanaka2012-05-151-1/+1
| | | | | | resolved. llvm-svn: 156801
* Turn off post-RA scheduler by default.Akira Hatanaka2012-03-281-1/+1
| | | | llvm-svn: 153557
* Turn on post register allocation scheduler.Akira Hatanaka2012-03-281-0/+12
| | | | llvm-svn: 153554
* remove blanks, and some code formatJia Liu2012-02-281-2/+2
| | | | llvm-svn: 151625
* remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.Jia Liu2012-02-171-1/+1
| | | | llvm-svn: 150805
* Unweaken vtables as per ↵David Blaikie2011-12-201-0/+2
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Change names for MIPS "generic" processors defined in Mips.td to match what GNUAkira Hatanaka2011-11-291-1/+1
| | | | | | | | | | tools use. Patch by Simon Atanasyan. "mips32r1" => "mips32" "4ke" => mips32r2" "mips64r1" => "mips64" llvm-svn: 145451
* Undo a change made in r140254.Akira Hatanaka2011-09-211-4/+4
| | | | | | MipsArchVersion needs to be initialized to Mips32. llvm-svn: 140261
* MipsArchVersion does not need to be in the initialization list and MipsABIAkira Hatanaka2011-09-211-1/+1
| | | | | | should be initialized to UnknownABI. llvm-svn: 140254
* Set ABI if it hasn't been set on the command line.Akira Hatanaka2011-09-211-0/+9
| | | | | | Check if architecture & ABI combination is valid. llvm-svn: 140230
* Drop support for Mips1 and Mips2.Akira Hatanaka2011-09-091-1/+1
| | | | llvm-svn: 139405
* Drop support for Allegrex. Allegrex implements a variant of Mips2.Akira Hatanaka2011-09-091-16/+0
| | | | llvm-svn: 139383
* Change default target architecture from Mips1 to Mips32r1 in preparation forAkira Hatanaka2011-09-091-2/+1
| | | | | | | | | removing support for Mips1 and Mips2. This change and the ones that follow have been discussed with and approved by Bruno. llvm-svn: 139344
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-14/+0
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-1/+1
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Change createAsmParser to take a MCSubtargetInfo instead of triple,Evan Cheng2011-07-091-0/+13
| | | | | | | | | CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. llvm-svn: 134795
* Eliminate asm parser's dependency on TargetMachine:Evan Cheng2011-07-081-1/+2
| | | | | | | | | | - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". llvm-svn: 134678
* Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng2011-07-071-2/+2
| | | | llvm-svn: 134606
* Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.Evan Cheng2011-07-011-1/+1
| | | | llvm-svn: 134281
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-011-1/+1
| | | | llvm-svn: 134259
* - Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng2011-07-011-0/+9
| | | | | | | | | itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. llvm-svn: 134257
* Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-301-4/+6
| | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! llvm-svn: 134127
* Reverse unnecessary changes made in r129606 and r129608. There is no change ↵Akira Hatanaka2011-04-151-3/+3
| | | | | | in functionality. llvm-svn: 129612
* Fix lines that have incorrect indentation or exceed 80 columns. There is no ↵Akira Hatanaka2011-04-151-3/+3
| | | | | | change in functionality. llvm-svn: 129606
* Remove (hopefully) all trailing whitespaces from the mips backend. Patch by ↵Bruno Cardoso Lopes2011-03-041-2/+2
| | | | | | Hatanaka, Akira llvm-svn: 127003
* reintroduce support for Mips "small" section handling. This is Chris Lattner2009-08-131-9/+0
| | | | | | | implemented somewhat differently than before, but it should have the same functionality and the previous testcase passes again. llvm-svn: 78900
* Restore some "small section" support code, reverting my patch from r76936.Chris Lattner2009-08-131-0/+8
| | | | llvm-svn: 78894
* Remove -disable-mips-abicall and -enable-mips-absolute-call command-line Eli Friedman2009-08-031-21/+5
| | | | | | | | | | | | | options, which don't appear to be useful. -enable-mips-absolute-call is completely unused (and unless I'm mistaken, is supposed to have the same effect that -relocation-model=dynamic-no-pic should have), and -disable-mips-abicall appears to be effectively a synonym for -relocation-model=static. Adjust the few users of hasABICall to checks which seem more appropriate. Update MipsSubtarget, MipsTargetMachine, and MipselTargetMachine to synchronize with recent changes. llvm-svn: 77938
* Normalize Subtarget constructors to take a target triple string instead ofDaniel Dunbar2009-08-021-3/+1
| | | | | | | | | | Module*. Also, dropped uses of TargetMachine where unnecessary. The only target which still takes a TargetMachine& is Mips, I would appreciate it if someone would normalize this to match other targets. llvm-svn: 77918
* remove more remnants of small section support.Chris Lattner2009-07-241-7/+0
| | | | llvm-svn: 76936
* Added support for fround, fextend and FP_TO_SINTBruno Cardoso Lopes2009-05-271-0/+1
| | | | llvm-svn: 72483
* Fixed Bug 2751Bruno Cardoso Lopes2008-09-151-3/+3
| | | | | | | | | | | http://llvm.org/bugs/show_bug.cgi?id=2751 Abicall was enabled even when static code model was provided in the command line. The correct behavior is to disable abicall when static is specified. llvm-svn: 56228
* Make option variables static, so they won't cause nameclashAnton Korobeynikov2008-08-221-7/+10
| | | | llvm-svn: 55203
* Removed SELECT_CC custom lowering. This is not needed anymore, the SELECT nodeBruno Cardoso Lopes2008-08-131-0/+2
| | | | | | | | | | | | | | | | is lowered properly and covers everything LowerSELECT_CC did. Added method printUnsignedImm in AsmPrinter to print uimm16 operands. This avoid the ugly instruction by instruction checking in printOperand. Added a swap instruction present in the allegrex core. Added two conditional instructions present in the allegrex core : MOVZ and MOVN. They both allow a more efficient SELECT operation for integers. Also added SELECT patterns to optimize MOVZ and MOVN usage. The brcond and setcc patterns were cleaned: redundant and suboptimal patterns were removed. The suboptimals were replaced by more efficient ones. Fixed some instructions that were using immZExt16 instead of immSExt16. llvm-svn: 54724
* Support added for ctlz intrinsic, test case added.Bruno Cardoso Lopes2008-08-081-0/+1
| | | | llvm-svn: 54516
* Match raw "psp" triple target, as done by the homebrew toolchain.Bruno Cardoso Lopes2008-08-081-1/+2
| | | | llvm-svn: 54514
* Added new features to represent specific instructions groupsBruno Cardoso Lopes2008-07-301-2/+3
| | | | llvm-svn: 54213
* Added initial support for small sections on Mips.Bruno Cardoso Lopes2008-07-211-0/+6
| | | | | | | Added gp_rel relocations to support addressing small section contents. Added command line to specify small section threshold in bytes. llvm-svn: 53869
* Added Subtarget support into RegisterInfoBruno Cardoso Lopes2008-07-141-2/+22
| | | | | | | | | | | | Added HasABICall and HasAbsoluteCall (equivalent to gcc -mabicall and -mno-shared). HasAbsoluteCall is not implemented but HasABICall is the default for o32 ABI. Now, both should help into a more accurate relocation types implementation. Added IsLinux is needed to choose between asm directives. Instruction name strings cleanup. AsmPrinter improved. llvm-svn: 53551
* Fixed features usage.Bruno Cardoso Lopes2008-07-091-3/+3
| | | | llvm-svn: 53277
* Several changes to Mips backend, experimental fp support being the mostBruno Cardoso Lopes2008-07-051-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
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