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* Revert "[DebugInfo] Add debug locations to constant SD nodes"Daniel Jasper2015-04-281-25/+21
| | | | | | | This breaks a test: http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/23870 llvm-svn: 235987
* [DebugInfo] Add debug locations to constant SD nodesSergey Dmitrouk2015-04-281-21/+25
| | | | | | | | | | | | | | | | | | | | | | | This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235977
* [mips] Support 9-bit offsets for the 'R' inline assembly memory constraint.Daniel Sanders2015-03-301-1/+14
| | | | | | | | | | | | | | | | | | | Summary: The 'R' constraint is actually supposed to be much more complicated than this and is defined in terms of whether it will cause macro expansion in the assembler. 'R' is getting less useful due to architecture changes and ought to be replaced by other constraints. We therefore implement 9-bit offsets which will work for all subtargets and all instructions. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8440 llvm-svn: 233537
* [mips] Support 16-bit offsets for 'm' inline assembly memory constraint.Daniel Sanders2015-03-241-1/+9
| | | | | | | | | | | | Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8435 llvm-svn: 233086
* [mips] Distinguish 'R', 'ZC', and 'm' inline assembly memory constraint.Daniel Sanders2015-03-241-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Previous behaviour of 'R' and 'm' has been preserved for now. They will be improved in subsequent commits. The offset permitted by ZC varies according to the subtarget since it is intended to match the restrictions of the pref, ll, and sc instructions. The restrictions on these instructions are: * For microMIPS: 12-bit signed offset. * For Mips32r6/Mips64r6: 9-bit signed offset. * Otherwise: 16-bit signed offset. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8414 llvm-svn: 233063
* [mips] Account for constant-zero operands in ADDE nodes.Vasileios Kalintiris2015-02-271-2/+6
| | | | | | | | | | | | | | | Summary: We identify the cases where the operand to an ADDE node is a constant zero. In such cases, we can avoid generating an extra ADDu instruction disguised as an identity move alias (ie. addu $r, $r, 0 --> move $r, $r). Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7906 llvm-svn: 230742
* [mips] Refactor and simplify MipsSEDAGToDAGISel::selectIntAddrLSL2MM(). NFC.Vasileios Kalintiris2015-02-131-9/+6
| | | | | | | | | | Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7618 llvm-svn: 229140
* [mips][microMIPS] Implement CodeGen support for SW16 and LW16 instructionsZoran Jovanovic2015-02-041-0/+25
| | | | | | Differential Revision: http://reviews.llvm.org/D6581 llvm-svn: 228149
* Get rid of a few calls through the subtarget to get the ABIEric Christopher2015-01-291-5/+5
| | | | | | that's actually sitting on the target machine. llvm-svn: 227513
* Remove most of the TargetMachine::getSubtarget/getSubtargetImplEric Christopher2015-01-291-2/+2
| | | | | | | | | calls that don't take a Function argument from Mips. Notable exceptions: the AsmPrinter and MipsTargetObjectFile. The latter needs to be fixed, and the former will be fixed when the general AsmPrinter changes happen. llvm-svn: 227512
* [mips] Enable arithmetic and binary operations for the i128 data type.Vasileios Kalintiris2015-01-261-4/+24
| | | | | | | | | | | | | | | | | | Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
* Revert "[mips] Fix assertion on i128 addition/subtraction on MIPS64"Vasileios Kalintiris2015-01-261-27/+5
| | | | | | | | This reverts commit r227003. Support for addition/subtraction and various other operations for the i128 data type will be added in a future commit based on the review D7143. llvm-svn: 227082
* [mips] Fix assertion on i128 addition/subtraction on MIPS64Daniel Sanders2015-01-241-5/+27
| | | | | | | | | | | | | | | | Summary: In addition to the included tests, this fixes test/CodeGen/Generic/i128-addsub.ll on a mips64 host. Reviewers: atanasyan, sagar, vmedic Reviewed By: vmedic Subscribers: sdkie, llvm-commits Differential Revision: http://reviews.llvm.org/D6610 llvm-svn: 227003
* Remove a bunch of unnecessary typecasts to 'const TargetRegisterClass *'Craig Topper2014-11-211-4/+1
| | | | llvm-svn: 222509
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-2/+1
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-1/+2
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* Fundamentally change the MipsSubtarget replacement machinery:Eric Christopher2014-07-181-0/+1
| | | | | | | | | | | | | | | | | a) Move the replacement level decision to the target machine. b) Create additional subtargets at the TargetMachine level to cache and make replacement easy. c) Make the mips16 features obvious. d) Remove the override logic as it no longer does anything. e) Have MipsModuleDAGToDAGISel take only the target machine. f) Have the constant islands pass grab the current subtarget from the MachineFunction (via the TargetMachine) instead of caching it. g) Unconditionally initialize TLOF. h) Remove the old complicated subtarget based resetting and replace it with simple conditionals. llvm-svn: 213430
* Make it possible for the Subtarget to change between functionEric Christopher2014-07-101-12/+12
| | | | | | | | passes in the mips back end. This, unfortunately, required a bit of churn in the various predicates to use a pointer rather than a reference. llvm-svn: 212744
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-6/+6
| | | | llvm-svn: 207197
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* [mips] Some uses of isMips64()/hasMips64() are really tests for 64-bit GPR'sDaniel Sanders2014-03-271-1/+1
| | | | | | | | | | | | Summary: No functional change since these predicates are (currently) synonymous. Extracted from a patch by David Chisnall His work was sponsored by: DARPA, AFRL Differential Revision: http://llvm-reviews.chandlerc.com/D3202 llvm-svn: 204943
* Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changingOwen Anderson2014-03-131-1/+1
| | | | | | | | | | operator* on the by-operand iterators to return a MachineOperand& rather than a MachineInstr&. At this point they almost behave like normal iterators! Again, this requires making some existing loops more verbose, but should pave the way for the big range-based for-loop cleanups in the future. llvm-svn: 203865
* [Modules] Move CFG.h to the IR library as it defines graph traits overChandler Carruth2014-03-041-1/+1
| | | | | | IR types. llvm-svn: 202827
* [mips] Prevent %lo relocation being used on MSA loads and stores.Daniel Sanders2014-03-031-38/+65
| | | | | | | | | | | | | | | | | Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 llvm-svn: 202717
* Re-sort all of the includes with ./utils/sort_includes.py so thatChandler Carruth2014-01-071-1/+1
| | | | | | | | | | subsequent changes are easier to review. About to fix some layering issues, and wanted to separate out the necessary churn. Also comment and sink the include of "Windows.h" in three .inc files to match the usage in Memory.inc. llvm-svn: 198685
* [mips] Fix 'ran out of registers' in MIPS32 with FP64 when generating code ↵Daniel Sanders2013-11-181-0/+5
| | | | | | | | | | for (ConstantFP 0.0) Fixed an inappropriate use of BuildPairF64 when compiling for MIPS32 with FP64 which resulted in an impossible constraint on the register allocation. It now uses BuildPairF64_64. llvm-svn: 195007
* [mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. ↵Daniel Sanders2013-11-121-0/+21
| | | | | | not intrinsics) llvm-svn: 194471
* [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. ↵Daniel Sanders2013-10-301-10/+64
| | | | | | | | | | | | | | | | | not intrinsics) This required correcting the definition of the bins[lr]i intrinsics because the result is also the first operand. It also required removing the (arbitrary) check for 32-bit immediates in MipsSEDAGToDAGISel::selectVSplat(). Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d because the constant is legalized into a ConstantPool. Similar things can happen with binsri.d with more than 10 bits set in the mask. The resulting code when this happens is correct but not optimal. llvm-svn: 193687
* [mips] Define a pseudo instruction which writes to both the lower and higherAkira Hatanaka2013-10-151-13/+0
| | | | | | parts of the accumulators and gets expanded post-RA. llvm-svn: 192667
* [mips] Rename isel nodes.Akira Hatanaka2013-10-151-1/+1
| | | | llvm-svn: 192663
* [mips][msa] Added support for matching splati from normal IR (i.e. not ↵Daniel Sanders2013-09-271-0/+10
| | | | | | | | intrinsics) Updated some of the vshf since they (correctly) emit splati's now llvm-svn: 191511
* [mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching ↵Daniel Sanders2013-09-241-0/+217
| | | | | | | | | | | | | | | | | | | | | | | | | | | BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
* Test commit to verify that commit access works.Zoran Jovanovic2013-09-131-1/+1
| | | | llvm-svn: 190676
* [mips][msa] Added load/store intrinsics.Daniel Sanders2013-08-281-0/+14
| | | | llvm-svn: 189476
* [mips][msa] Added move.vDaniel Sanders2013-08-281-0/+16
| | | | llvm-svn: 189471
* [mips][msa] Added cfcmsa, and ctcmsaDaniel Sanders2013-08-281-0/+48
| | | | | | | | The MSA control registers have been added as reserved registers, and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered into these nodes. llvm-svn: 189468
* [Mips] Support for unaligned load/store microMips instructionsJack Carter2013-08-131-0/+31
| | | | | | | | This includes instructions lwl, lwr, swl and swr. Patch by Zoran Jovnovic llvm-svn: 188312
* [mips] Rename accumulator register classes and FP register operands.Akira Hatanaka2013-08-081-2/+2
| | | | llvm-svn: 188020
* [mips] Delete register class HWRegs64.Akira Hatanaka2013-08-081-4/+2
| | | | | | No functionality change. llvm-svn: 188016
* [mips] Rename register classes CPURegs and CPU64Regs.Akira Hatanaka2013-08-061-2/+2
| | | | llvm-svn: 187832
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-191-1/+1
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184360
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-061-1/+1
| | | | | | | Caching it as a pointer allows us to reset it if the TargetMachine object changes. llvm-svn: 183361
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-251-4/+4
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* [mips] Split the DSP control register and define one register for each field ofAkira Hatanaka2013-05-031-2/+33
| | | | | | | | | | | its fields. This removes false dependencies between DSP instructions which access different fields of the the control register. Implicit register operands are added to instructions RDDSP and WRDSP after instruction selection, depending on the value of the mask operand. llvm-svn: 181041
* ArrayRefize getMachineNode(). No functionality change.Michael Liao2013-04-191-2/+2
| | | | llvm-svn: 179901
* [mips] Reapply r179420 and r179421.Akira Hatanaka2013-04-131-0/+2
| | | | llvm-svn: 179434
* Revert r179420 and r179421.Akira Hatanaka2013-04-121-2/+0
| | | | llvm-svn: 179422
* [mips] Instruction selection patterns for carry-setting and using addAkira Hatanaka2013-04-121-0/+2
| | | | | | instructions. llvm-svn: 179421
* [mips] Custom-lower i64 MULHS and MULHU nodes. Remove the code which selectsAkira Hatanaka2013-04-111-63/+0
| | | | | | | | multiply instructions in MipsSEDAGToDAGISel. This patch was supposed to be part of r178403. llvm-svn: 179314
* This patch enables llvm to switch between compiling for mips32/mips64 Reed Kotler2013-04-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and mips16 on a per function basis. Because this patch is somewhat involved I have provide an overview of the key pieces of it. The patch is written so as to not change the behavior of the non mixed mode. We have tested this a lot but it is something new to switch subtargets so we don't want any chance of regression in the mainline compiler until we have more confidence in this. Mips32/64 are very different from Mip16 as is the case of ARM vs Thumb1. For that reason there are derived versions of the register info, frame info, instruction info and instruction selection classes. Now we register three separate passes for instruction selection. One which is used to switch subtargets (MipsModuleISelDAGToDAG.cpp) and then one for each of the current subtargets (Mips16ISelDAGToDAG.cpp and MipsSEISelDAGToDAG.cpp). When the ModuleISel pass runs, it determines if there is a need to switch subtargets and if so, the owning pointers in MipsTargetMachine are appropriately changed. When 16Isel or SEIsel is run, they will return immediately without doing any work if the current subtarget mode does not apply to them. In addition, MipsAsmPrinter needs to be reset on a function basis. The pass BasicTargetTransformInfo is substituted with a null pass since the pass is immutable and really needs to be a function pass for it to be used with changing subtargets. This will be fixed in a follow on patch. llvm-svn: 179118
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