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* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-281-3/+3
| | | | | | | getFrameInfo() never returns nullptr so we should use a reference instead of a pointer. llvm-svn: 277017
* [mips][mips16] Fix machine verifier errors about incorrect register classes ↵Daniel Sanders2016-06-161-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on load/stores. Summary: [ls][bh] and [ls][bh]u cannot use sp-relative addresses and must therefore lower frameindex nodes such that there is a copy to a CPU16Regs register. This is now done consistently using a separate addressing mode that does not permit frameindex nodes. As part of this I've had to remove an optimization that reduced the number of instructions needed to work around the lack of sp-relative addresses on [ls][bh] and [ls][bh]u. This optimization used one of the eight CPU16Regs registers as a copy of the stack pointer and it's implementation was the root cause of many of the register vs register class mismatches. lw/sw can use sp-relative addresses but we ought to ensure that we use the correct version of lw/sw internally for things like IAS. This is not currently the case and this change does not fix this. However, this change does clean it up sufficiently well to fix the machine verifier failures. Also removed irrelevant functions from stchar.ll. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21062 llvm-svn: 272882
* [mips][microMIPS] Fix for "Cannot copy registers" assertionHrvoje Varga2016-04-131-1/+3
| | | | | | | | Differential Revision: http://reviews.llvm.org/D17068 This changes contains fix for failing test-suite. So, this patch should hopefully work now. llvm-svn: 266171
* [mips][microMIPS] Revert commits r264245 and r264248.Zoran Jovanovic2016-04-021-3/+1
| | | | | | | Commit r264245 was the reason for failing tests in LLVM test suite. Commit r264248 depends on the first one. llvm-svn: 265249
* [mips][microMIPS] Fix for "Cannot copy registers" assertionHrvoje Varga2016-03-241-1/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D17068 llvm-svn: 264245
* [mips] Interrupt attribute support for mips32r2+.Vasileios Kalintiris2015-10-261-0/+15
| | | | | | | | | | | | | | | | | | | Summary: This patch adds support for using the "interrupt" attribute on Mips for interrupt handling functions. At this time only mips32r2+ with the o32 ABI with the static relocation model is supported. Unsupported configurations will be rejected Patch by Simon Dardis (+ clang-format & some trivial changes to follow the LLVM coding standards by me). Reviewers: mpf, dsanders Subscribers: dsanders, vkalintiris, llvm-commits Differential Revision: http://reviews.llvm.org/D10768 llvm-svn: 251286
* PseudoSourceValue: Transform the mips subclass to target independent subclassesAlex Lorenz2015-08-111-51/+4
| | | | | | | | | | | | This commit transforms the mips-specific 'MipsCallEntry' subclass of the 'PseudoSourceValue' class into two, target-independent subclasses named 'GlobalValuePseudoSourceValue' and 'ExternalSymbolPseudoSourceValue'. This change makes it easier to serialize the pseudo source values by removing target-specific pseudo source values. Reviewers: Akira Hatanaka llvm-svn: 244698
* PseudoSourceValue: Introduce a 'PSVKind' enumerator.Alex Lorenz2015-08-111-2/+3
| | | | | | | | | | | | | | This commit introduces a new enumerator named 'PSVKind' in the 'PseudoSourceValue' class. This enumerator is now used to distinguish between the various kinds of pseudo source values. This change is done in preparation for the changes to the pseudo source value object management and to the PseudoSourceValue's class hierarchy - the next two PseudoSourceValue commits will get rid of the global variable that manages the pseudo source values and the mips specific MipsCallEntry subclass. Reviewers: Akira Hatanaka llvm-svn: 244687
* [Mips] Use unique_ptr to manage ownership.Benjamin Kramer2015-04-161-15/+7
| | | | | | | Required some tweaking of ValueMap to accommodate a move-only value type. No functional change intended. llvm-svn: 235091
* [mips][microMIPS] Change register class for GP registerZoran Jovanovic2015-02-271-6/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D7934 llvm-svn: 230760
* Re-sort #include lines using my handy dandy ./utils/sort_includes.pyChandler Carruth2015-02-131-1/+1
| | | | | | script. This is in preparation for changes to lots of include lines. llvm-svn: 229088
* Remove most of the TargetMachine::getSubtarget/getSubtargetImplEric Christopher2015-01-291-9/+13
| | | | | | | | | calls that don't take a Function argument from Mips. Notable exceptions: the AsmPrinter and MipsTargetObjectFile. The latter needs to be fixed, and the former will be fixed when the general AsmPrinter changes happen. llvm-svn: 227512
* Remove a bunch of unnecessary typecasts to 'const TargetRegisterClass *'Craig Topper2014-11-211-9/+5
| | | | llvm-svn: 222509
* Fix some cases where StringRef was being passed by const reference. Remove ↵Craig Topper2014-08-301-2/+2
| | | | | | const from some other StringRefs since its implicitly const already. llvm-svn: 216820
* [mips] For the FP64A ABI, odd-numbered double-precision moves must not use ↵Daniel Sanders2014-07-141-5/+5
| | | | | | | | | | | | | | | | | | | | | mtc1/mfc1. Summary: This is because the FP64A the hardware will redirect 32-bit reads/writes from/to odd-numbered registers to the upper 32-bits of the corresponding even register. In effect, simulating FR=0 mode when FR=0 mode is not available. Unfortunately, we have to make the decision to avoid mfc1/mtc1 before register allocation so we currently do this for even registers too. FPXX has a similar requirement on 32-bit architectures that lack mfhc1/mthc1 so this patch also handles the affected moves from the FPU for FPXX too. Moves to the FPU were supported by an earlier commit. Differential Revision: http://reviews.llvm.org/D4484 llvm-svn: 212938
* [mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI isSasa Stankovic2014-07-141-0/+8
| | | | | | | | | | | | | | | enabled and mthc1 and dmtc1 are not available (e.g. on MIPS32r1) This prevents the upper 32-bits of a double precision value from being moved to the FPU with mtc1 to an odd-numbered FPU register. This is necessary to ensure that the code generated executes correctly regardless of the current FPU mode. MIPS32r2 and above continues to use mtc1/mthc1, while MIPS-IV and above continue to use dmtc1. Differential Revision: http://reviews.llvm.org/D4465 llvm-svn: 212930
* Use range loop.Rafael Espindola2014-05-071-3/+2
| | | | llvm-svn: 208218
* [C++] Use 'nullptr'.Craig Topper2014-04-281-1/+1
| | | | llvm-svn: 207394
* [mips] Simplify and optimize code.Akira Hatanaka2013-10-081-10/+6
| | | | | | No intended functionality change. llvm-svn: 192213
* MipsMachineFunction.cpp: Add missing #include <raw_ostream.h>NAKAMURA Takumi2013-09-281-0/+1
| | | | llvm-svn: 191597
* [mips] Define a derived class of PseudoSourceValue that represents a GOT entryAkira Hatanaka2013-09-271-0/+69
| | | | | | resolved by lazy-binding. llvm-svn: 191578
* [mips] Rename register classes CPURegs and CPU64Regs.Akira Hatanaka2013-08-061-3/+3
| | | | llvm-svn: 187832
* [mips] Lower EH_RETURN.Akira Hatanaka2013-01-301-0/+16
| | | | | | Patch by Sasa Stankovic. llvm-svn: 173862
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-1/+1
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-2/+2
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* This patch is for the implementation of mips16 complex pattern addr16.Reed Kotler2012-10-281-0/+13
| | | | | | | | | | | | | | | | | | | | | Previously mips16 was sharing the pattern addr which is used for mips32 and mips64. This had a number of problems: 1) Storing and loading byte and halfword quantities for mips16 has particular problems due to the primarily non mips16 nature of SP. When we must load/store byte/halfword stack objects in a function, we must create a mips16 alias register for SP. This functionality is tested in stchar.ll. 2) We need to have an FP register under certain conditions (such as dynamically sized alloca). We use mips16 register S0 for this purpose. In this case, we also use this register when accessing frame objects so this issue also affects the complex pattern addr16. This functionality is tested in alloca16.ll. The Mips16InstrInfo.td has been updated to use addr16 instead of addr. The complex pattern C++ function for addr has been copied to addr16 and updated to reflect the above issues. llvm-svn: 166897
* Add basic ability to setup call frame, and make procedure calls.Akira Hatanaka2012-07-231-4/+7
| | | | | | | | Hello world will compile and execute with this patch. Patch by Reed Kotler. llvm-svn: 160651
* Revert accidental commit.Akira Hatanaka2012-07-211-7/+4
| | | | llvm-svn: 160598
* Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind.Akira Hatanaka2012-07-211-4/+7
| | | | | | Test case will be added later when long branch patch is checked in. llvm-svn: 160597
* Delete all functions that are no longer needed in MipsFunctionInfo, includingAkira Hatanaka2012-05-121-7/+0
| | | | | | | | | the ones that get or set the frame index for the $gp save slot. Remove the piece of code in MipsFunctionInfo::getGlobalBaseReg() which returns GP. This function should always return a virtual register. llvm-svn: 156695
* Do not use $gp as a dedicated global register if the target ABI is not O32. Akira Hatanaka2012-04-251-2/+2
| | | | llvm-svn: 155522
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-3/+3
| | | | | | since they are equivalent. llvm-svn: 155188
* remove blanks, and some code formatJia Liu2012-02-281-1/+1
| | | | llvm-svn: 151625
* Add an option to use a virtual register as the global base register instead ofAkira Hatanaka2012-02-241-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... llvm-svn: 151402
* remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.Jia Liu2012-02-171-1/+1
| | | | llvm-svn: 150805
* Unweaken vtables as per ↵David Blaikie2011-12-201-0/+14
http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
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