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* [mips][msa] Correct sld and sldi builtins.Daniel Sanders2013-12-101-13/+21
| | | | | | | | | | | | | Summary: The result register of these instructions is also the first operand. Reviewers: jacksprat, dsanders Reviewed By: dsanders Differential Revision: http://llvm-reviews.chandlerc.com/D2362 Differential Revision: http://llvm-reviews.chandlerc.com/D2363 llvm-svn: 196910
* [mips][msa] Fix issue with immediate fields of LD/ST instructionsMatheus Almeida2013-12-051-2/+2
| | | | | | | | | not being correctly encoded/decoded. In more detail, immediate fields of LD/ST instructions should be divided/multiplied by the size of the data format before encoding and after decoding, respectively. llvm-svn: 196494
* [mips][msa] Pseudo instructions require HasMSA too. Inherit from MSAPseudo ↵Daniel Sanders2013-11-201-17/+17
| | | | | | | | | | | instead of MipsPseudo There's no test case for this commit. This is because it is doubtful that the incorrect behaviour can actually trigger. When MSA is not enabled, the type legalizer should have eliminated all occurrences of patterns the affected pseudo-instruction could possibly match before instruction selection occurs. llvm-svn: 195252
* [mips][msa] Remove unused instruction class MSA_I8_X_DESC_BASEDaniel Sanders2013-11-201-11/+0
| | | | llvm-svn: 195245
* long line correctionJack Carter2013-11-201-4/+8
| | | | llvm-svn: 195175
* [mips][msa] Update encoding of bnz.v (typo).Matheus Almeida2013-11-181-1/+1
| | | | | | Note that there's no hardware yet that relies on that encoding. llvm-svn: 195006
* [mips][msa] Fix immediate value of LSA instruction as it was being wrongly ↵Matheus Almeida2013-11-181-1/+16
| | | | | | | | | encoded. The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field. llvm-svn: 195004
* [mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. ↵Daniel Sanders2013-11-121-38/+65
| | | | | | not intrinsics) llvm-svn: 194471
* [mips][msa] Added support for matching bset, bseti, bneg, and bnegi from ↵Daniel Sanders2013-11-121-70/+147
| | | | | | normal IR (i.e. not intrinsics) llvm-svn: 194469
* [mips][msa] Update encoding of LDI instruction.Matheus Almeida2013-11-081-4/+4
| | | | | | The encoding was updated in MSA r1.07. llvm-svn: 194255
* [mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related testsDaniel Sanders2013-10-301-8/+29
| | | | llvm-svn: 193695
* [mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from ↵Daniel Sanders2013-10-301-5/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | normal IR (i.e. not intrinsics) Also corrected the definition of the intrinsics for these instructions (the result register is also the first operand), and added intrinsics for bsel and bseli to clang (they already existed in the backend). These four operations are mostly equivalent to bsel, and bseli (the difference is which operand is tied to the result). As a result some of the tests changed as described below. bitwise.ll: - bsel.v test adapted so that the mask is unknown at compile-time. This stops it emitting bmnzi.b instead of the intended bsel.v. - The bseli.b test now tests the right thing. Namely the case when one of the values is an uimm8, rather than when the condition is a uimm8 (which is covered by bmnzi.b) compare.ll: - bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this is the same operation (see MSA.txt). i8.ll - CHECK-DAG-ized test. - bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands because this is the same operation (see MSA.txt). - bseli.b still emits bseli.b though because the immediate makes it distinguishable from bmnzi.b. vec.ll: - CHECK-DAG-ized test. - bmz.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). - bsel.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). llvm-svn: 193693
* [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. ↵Daniel Sanders2013-10-301-16/+45
| | | | | | | | | | | | | | | | | not intrinsics) This required correcting the definition of the bins[lr]i intrinsics because the result is also the first operand. It also required removing the (arbitrary) check for 32-bit immediates in MipsSEDAGToDAGISel::selectVSplat(). Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d because the constant is legalized into a ConstantPool. Similar things can happen with binsri.d with more than 10 bits set in the mask. The resulting code when this happens is correct but not optimal. llvm-svn: 193687
* [mips][msa] Added support for matching splat.[bhw] from normal IR (i.e. not ↵Daniel Sanders2013-10-301-26/+36
| | | | | | | | | | intrinsics) splat.d is implemented but this subtest is currently disabled. This is because it is difficult to match the appropriate IR on MIPS32. There is a patch under review that should help with this so I hope to enable the subtest soon. llvm-svn: 193680
* [mips][msa] Direct Object Emission support for the LSA instruction.Matheus Almeida2013-10-231-5/+6
| | | | llvm-svn: 193240
* [mips][msa] Added support for matching fexp2 from normal IR (i.e. not ↵Daniel Sanders2013-10-231-4/+18
| | | | | | intrinsics) llvm-svn: 193239
* [mips][msa] Direct Object Emission support for conditional branches.Matheus Almeida2013-10-221-23/+23
| | | | | | | | | | | | These branches have a 16-bit offset (R_MIPS_PC16). List of conditional branch instructions: bnz.{b,h,w,d} bnz.v bz.{b,h,w,d} bz.v llvm-svn: 193157
* [mips][msa] Direct Object Emission support for LD/ST instructions.Matheus Almeida2013-10-211-24/+26
| | | | llvm-svn: 193082
* [mips][msa] Direct Object Emission support for LDI instructions.Matheus Almeida2013-10-211-8/+8
| | | | llvm-svn: 193081
* [mips][msa] Direct Object Emission support for MOVE.v.Matheus Almeida2013-10-211-2/+2
| | | | llvm-svn: 193080
* [mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. Matheus Almeida2013-10-211-5/+5
| | | | | | | | These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. llvm-svn: 193078
* [mips][msa] Direct Object Emission of SPLAT instruction.Matheus Almeida2013-10-211-12/+16
| | | | llvm-svn: 193077
* [mips][msa] Fix definition of SLD instruction.Matheus Almeida2013-10-211-8/+23
| | | | | | | The second parameter of the SLD intrinsic is the number of columns (GPR) to slide left the source array. llvm-svn: 193076
* [mips][msa] Added lsa instructionDaniel Sanders2013-10-171-0/+18
| | | | llvm-svn: 192895
* [mips][msa] Removed ldx.[bhwd] and stx.[bhwd].Daniel Sanders2013-10-171-51/+0
| | | | | | | | These were present in a previous version of the MSA spec but are not present in the published version. There is no hardware that uses these instructions. llvm-svn: 192888
* [mips][msa] Correct definition order of ftrunc_[su], ftint_[su], and ftq.Daniel Sanders2013-10-171-22/+22
| | | | | | | | Define these three instructions in alphabetical order (like the rest of the file). No functional change. llvm-svn: 192880
* [mips][msa] Added support for build_vector for v4f32 and v2f64.Daniel Sanders2013-10-151-3/+22
| | | | llvm-svn: 192699
* [mips][msa] Direct Object Emission support for BIT instructions.Matheus Almeida2013-10-141-74/+102
| | | | | | | | | | | | | | | | | | List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
* [mips][msa] Direct Object Emission support for VEC instructions.Matheus Almeida2013-10-141-67/+81
| | | | | | | List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
* [mips][msa] Direct Object Emission of INSVE.{b,h,w,d}.Matheus Almeida2013-10-141-14/+18
| | | | llvm-svn: 192587
* [mips][msa] Direct Object Emission for the majority of the ELM instructions.Matheus Almeida2013-10-141-31/+42
| | | | | | | | | | List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
* [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.Matheus Almeida2013-10-141-14/+14
| | | | | | | | | INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. llvm-svn: 192582
* This reverts 192447 because of compiler warning generated on darwin build.Matheus Almeida2013-10-111-14/+14
| | | | llvm-svn: 192451
* This reverts r192449 because of compiler warning generated on darwin build.Matheus Almeida2013-10-111-42/+31
| | | | llvm-svn: 192450
* [mips][msa] Direct Object Emission for the majority of the ELM instructions.Matheus Almeida2013-10-111-31/+42
| | | | llvm-svn: 192449
* [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.Matheus Almeida2013-10-111-14/+14
| | | | | | | | INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. llvm-svn: 192447
* [mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from ↵Daniel Sanders2013-10-111-16/+15
| | | | | | normal IR (i.e. not intrinsics) llvm-svn: 192438
* [mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not ↵Daniel Sanders2013-10-111-4/+4
| | | | | | intrinsics) llvm-svn: 192435
* [mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not ↵Daniel Sanders2013-10-111-4/+2
| | | | | | intrinsics) llvm-svn: 192430
* [mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] ↵Daniel Sanders2013-10-111-12/+8
| | | | | | from normal IR (i.e. not intrinsics) llvm-svn: 192429
* [mips][msa] Added support for matching mod_[us] from normal IR (i.e. not ↵Daniel Sanders2013-10-011-9/+9
| | | | | | intrinsics) llvm-svn: 191737
* [mips][msa] Direct Object Emission for I8 instructions.Jack Carter2013-09-301-28/+32
| | | | | | | | | This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
* [mips][msa] Direct Object Emission for I5 instructions.Jack Carter2013-09-301-49/+57
| | | | | | | | | This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
* [mips][msa] Direct Object Emission for 2R instructions.Jack Carter2013-09-301-16/+16
| | | | | | | | | This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}. Patch by Matheus Almeida llvm-svn: 191685
* [PATCH 1/4] [mips][msa] Source register of FILL instructions is GPRJack Carter2013-09-301-15/+15
| | | | | | | | and not an MSA register Patch by Matheus Almeida llvm-svn: 191684
* [mips][msa] Rename arguments to MSA_INSERT_DESC_BASE to better match their ↵Daniel Sanders2013-09-271-6/+6
| | | | | | | | expected values. No functional change. llvm-svn: 191517
* [mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.Daniel Sanders2013-09-271-0/+20
| | | | | | | For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. llvm-svn: 191515
* [mips][msa] Implemented extract_vector_elt for v4f32 or v2f64Daniel Sanders2013-09-271-0/+15
| | | | | | | For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. llvm-svn: 191514
* [mips][msa] Added support for matching splati from normal IR (i.e. not ↵Daniel Sanders2013-09-271-8/+44
| | | | | | | | intrinsics) Updated some of the vshf since they (correctly) emit splati's now llvm-svn: 191511
* [mips][msa] Direct Object Emission for 3RF instructions.Jack Carter2013-09-261-112/+117
| | | | | | Patch by Matheus Almeida llvm-svn: 191461
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