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* [mips][msa] Updates encoding of 3RF instructions to match the latest ↵Jack Carter2013-09-261-2/+2
| | | | | | | | | | revision of the MSA spec (1.06). This does not affect any of the existing output. Patch by Matheus Almeida llvm-svn: 191460
* [mips][msa] Direct Object Emission for 3R instructions.Jack Carter2013-09-261-330/+378
| | | | | | | | This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
* [mips][msa] Updates encoding of 3R instructions to match the latest revision ↵Jack Carter2013-09-261-9/+9
| | | | | | | | | | | of the MSA spec (1.06). Internal changes only. Patch by Matheus Almeida llvm-svn: 191414
* [mips][msa] Direct Object Emission for 2RF instructions.Jack Carter2013-09-251-41/+36
| | | | | | Patch by Matheus Almeida llvm-svn: 191413
* [mips][msa] Direct Object Emission support for the MSA instruction set. Jack Carter2013-09-251-4/+13
| | | | | | | | | | In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida llvm-svn: 191412
* [mips][msa] Updates encoding of 2RF instructions to match the latest ↵Jack Carter2013-09-251-4/+4
| | | | | | | | | | | | revision of the MSA spec (1.06). This only changes internal encodings and doesn't affect output. Patch by Matheus Almeida llvm-svn: 191411
* [mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. ↵Daniel Sanders2013-09-241-8/+10
| | | | | | not intrinsics) llvm-svn: 191306
* [mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal ↵Daniel Sanders2013-09-241-19/+25
| | | | | | IR (i.e. not intrinsics) llvm-svn: 191304
* [mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-241-3/+16
| | | | llvm-svn: 191302
* [mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-241-4/+21
| | | | llvm-svn: 191301
* [mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching ↵Daniel Sanders2013-09-241-178/+263
| | | | | | | | | | | | | | | | | | | | | | | | | | | BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
* [mips][msa] Added partial support for matching fmax_a from normal IR (i.e. ↵Daniel Sanders2013-09-241-0/+14
| | | | | | | | not intrinsics) This covers the case where fmax_a can be used to implement ISD::FABS. llvm-svn: 191296
* [mips][msa] Line wrapping.Daniel Sanders2013-09-241-4/+4
| | | | | | No functional change. llvm-svn: 191295
* [mips][msa] Added support for matching andi, ori, nori, and xori from normal ↵Daniel Sanders2013-09-241-10/+23
| | | | | | IR (i.e. not intrinsics) llvm-svn: 191293
* [mips][msa] Added support for matching max, maxi, min, mini from normal IR ↵Daniel Sanders2013-09-241-59/+56
| | | | | | (i.e. not intrinsics) llvm-svn: 191291
* [mips][msa] Added support for matching bsel and bseli from normal IR (i.e. ↵Daniel Sanders2013-09-241-2/+33
| | | | | | | | not intrinsics) This required correcting the definition of the bsel and bseli intrinsics. llvm-svn: 191290
* [mips][msa] Added support for matching comparisons from normal IR (i.e. not ↵Daniel Sanders2013-09-241-73/+152
| | | | | | | | | intrinsics) MIPS SelectionDAG changes: * Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask. llvm-svn: 191286
* [mips][msa] Added support for matching slli, srai, and srli from normal IR ↵Daniel Sanders2013-09-241-20/+72
| | | | | | (i.e. not intrinsics) llvm-svn: 191285
* [mips][msa] Added support for matching addvi, and subvi from normal IR (i.e. ↵Daniel Sanders2013-09-231-25/+46
| | | | | | not intrinsics) llvm-svn: 191203
* [mips][msa] Added support for matching insert and copy from normal IR (i.e. ↵Daniel Sanders2013-09-231-18/+48
| | | | | | | | | | | not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. llvm-svn: 191199
* [mips][msa] Added support for matching pcnt from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-231-4/+4
| | | | llvm-svn: 191198
* [mips][msa] Added support for matching nor from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-231-1/+15
| | | | llvm-svn: 191195
* [mips][msa] Added support for matching and, or, and xor from normal IR (i.e. ↵Daniel Sanders2013-09-231-3/+45
| | | | | | not intrinsics) llvm-svn: 191194
* [mips][msa] Implemented build_vector using ldi, fill, and custom ↵Daniel Sanders2013-09-231-10/+16
| | | | | | | | | | | | | | | | | | SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal llvm-svn: 191191
* [mips][msa] Added support for matching mulv, nlzc, sll, sra, srl, and subv ↵Daniel Sanders2013-09-111-24/+24
| | | | | | from normal IR (i.e. not intrinsics) llvm-svn: 190518
* [mips][msa] Added support for matching fadd, fdiv, flog2, fmul, frint, ↵Daniel Sanders2013-09-111-16/+14
| | | | | | fsqrt, and fsub from normal IR (i.e. not intrinsics) llvm-svn: 190512
* [mips][msa] Added support for matching div_[su] from normal IR (i.e. not ↵Daniel Sanders2013-09-111-9/+9
| | | | | | intrinsics) llvm-svn: 190509
* [mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-111-8/+5
| | | | | | The corresponding intrinsic is now lowered into equivalent IR (ISD::ADD) before instruction selection. llvm-svn: 190507
* [mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsicsDaniel Sanders2013-09-111-13/+13
| | | | | | | The elements of the operands should be half the width of the elements of the result. llvm-svn: 190505
* [mips][msa] Removed unsupported dot product instructions (dotp_[su].b)Daniel Sanders2013-09-101-8/+0
| | | | | | The dotp_[su].b instructions never existed in any revision of the MSA spec. llvm-svn: 190398
* [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fitAkira Hatanaka2013-09-071-4/+0
| | | | | | into a 5-bit or 6-bit field. llvm-svn: 190226
* [mips][msa] IndentationDaniel Sanders2013-09-061-34/+34
| | | | llvm-svn: 190156
* [mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritanceDaniel Sanders2013-09-061-628/+628
| | | | | | | Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
* [mips][msa] Made the operand register sets optional for the VEC formatsDaniel Sanders2013-09-061-16/+9
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190153
* [mips][msa] Made the operand register sets optional for the ELM_INSVE formatsDaniel Sanders2013-09-061-14/+10
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190151
* [mips][msa] Made the operand register sets optional for the 3RF_4RF formatDaniel Sanders2013-09-061-14/+14
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190150
* [mips][msa] Made the operand register sets optional for the 3RF formatsDaniel Sanders2013-09-061-132/+72
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190146
* [mips][msa] Made the operand register sets optional for the 3R_4R formatDaniel Sanders2013-09-061-30/+22
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190145
* [mips][msa] Made the operand register sets optional for the 2RF formatDaniel Sanders2013-09-061-59/+39
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190143
* [mips][msa] Made the operand register sets optional for the I8 formatDaniel Sanders2013-09-061-21/+12
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190142
* [mips][msa] Made the operand register sets optional for the I5 and SI5 formatsDaniel Sanders2013-09-061-74/+46
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190141
* [mips][msa] Made the operand register sets optional for the BIT_[BHWD] formatsDaniel Sanders2013-09-061-104/+60
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190140
* [mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element sizeDaniel Sanders2013-09-061-16/+16
| | | | | | No functional change llvm-svn: 190134
* [mips][msa] Made the operand register sets optional for the 3R formatDaniel Sanders2013-09-061-460/+280
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190133
* [mips][msa] Made the InstrItinClass argument optional since it is always ↵Daniel Sanders2013-09-061-600/+607
| | | | | | | | NoItinerary at the moment. No functional change llvm-svn: 190131
* [mips][msa] Added bnz.df, bnz.v, bz.df, and bz.vDaniel Sanders2013-08-281-1/+94
| | | | | | | | | | | | | These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
* [mips][msa] Added load/store intrinsics.Daniel Sanders2013-08-281-20/+89
| | | | llvm-svn: 189476
* [mips][msa] Added move.vDaniel Sanders2013-08-281-0/+12
| | | | llvm-svn: 189471
* [mips][msa] Added cfcmsa, and ctcmsaDaniel Sanders2013-08-281-0/+24
| | | | | | | | The MSA control registers have been added as reserved registers, and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered into these nodes. llvm-svn: 189468
* [mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ↵Daniel Sanders2013-08-281-14/+327
| | | | | | ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
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