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path: root/llvm/lib/Target/Mips/MipsMCInstLower.cpp
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* Emit all directives except for ".cprestore" during asm printing rather than emitAkira Hatanaka2012-03-281-63/+57
| | | | | | | | | | | | | | | | them as machine instructions. Directives ".set noat" and ".set at" are now emitted only at the beginning and end of a function except in the case where they are emitted to enclose .cpload with an immediate operand that doesn't fit in 16-bit field or unaligned load/stores. Also, make the following changes: - Remove function isUnalignedLoadStore and use a switch-case statement to determine whether an instruction is an unaligned load or store. - Define helper function CreateMCInst which generates an instance of an MCInst from an opcode and a list of operands. llvm-svn: 153552
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-1/+1
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* remove blanks, and some code formatJia Liu2012-02-281-9/+9
| | | | llvm-svn: 151625
* Add an option to use a virtual register as the global base register instead ofAkira Hatanaka2012-02-241-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... llvm-svn: 151402
* remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.Jia Liu2012-02-171-1/+1
| | | | llvm-svn: 150805
* add Emacs tag and fix some comment error in file headersJia Liu2012-02-171-1/+1
| | | | llvm-svn: 150775
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-5/+3
| | | | llvm-svn: 149961
* Ignore register mask operands when lowering instructions to MC.Jakob Stoklund Olesen2012-01-181-0/+2
| | | | | | | This is similar to implicit register operands. MC doesn't understand register liveness and call clobbers. llvm-svn: 148437
* Cleanup Mips code and rename some variables. Patch by Jack CarterBruno Cardoso Lopes2011-12-301-73/+73
| | | | llvm-svn: 147383
* Tidy up. Simplify logic. No functional change intended.Akira Hatanaka2011-12-191-20/+20
| | | | llvm-svn: 146896
* Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct objectAkira Hatanaka2011-12-141-0/+3
| | | | | | | emission is not supported yet, but a patch that adds the support should follow soon. llvm-svn: 146572
* Expand .cprestore directive to multiple instructions if the offset does not fit Akira Hatanaka2011-12-131-6/+27
| | | | | | in a 16-bit field. llvm-svn: 146469
* Add a few moreLocal/Global R_MIPS_GOT related fixups andBruno Cardoso Lopes2011-12-071-0/+1
| | | | | | | | make the addend fixup code a bit more generic Patch by Jack Carter. llvm-svn: 145998
* This patch makes the following changes necessary for MIPS' direct code emission.Akira Hatanaka2011-11-231-32/+146
| | | | | | | | - lower unaligned loads/stores. - encode the size operand of instructions INS and EXT. - emit relocation information needed for JAL (jump-and-link). llvm-svn: 145113
* Mips MC object code emission improvements:Bruno Cardoso Lopes2011-11-111-0/+1
| | | | | | | | | | "With this patch we can now generate runnable Mips code through LLVM direct object emission. We have run numerous simple programs, both C and C++ and with -O0 and -O3 from the output. The code is not production ready, but quite useful for experimentation." Patch and message by Jack Carter llvm-svn: 144414
* Properly handle Mips MC relocations and lower cpload and cprestore macros to ↵Bruno Cardoso Lopes2011-11-081-20/+77
| | | | | | | | MCInsts. Patch by Jack Carter. llvm-svn: 144139
* Add enums and functions for symbols Mips64 uses.Akira Hatanaka2011-09-221-0/+5
| | | | llvm-svn: 140295
* Drop support for Mips1 and Mips2.Akira Hatanaka2011-09-091-44/+0
| | | | llvm-svn: 139405
* Fix handling of double precision loads and stores when Mips1 is targeted. Akira Hatanaka2011-08-161-0/+44
| | | | | | | | | | | | | | | Mips1 does not support double precision loads or stores, therefore two single precision loads or stores must be used in place of these instructions. This patch treats double precision loads and stores as if they are legal instructions until MCInstLowering, instead of generating the single precision instructions during instruction selection or Prolog/Epilog code insertion. Without the changes made in this patch, llc produces code that has the same problem described in r137484 or bails out when MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before register allocation. llvm-svn: 137711
* Define function MipsMCInstLower::LowerOperand. Akira Hatanaka2011-08-161-25/+28
| | | | llvm-svn: 137707
* Add parameter Offset to MipsMCInstLower::LowerSymbolOperand. Akira Hatanaka2011-08-161-4/+4
| | | | llvm-svn: 137706
* Raise assertion when MachineOperand has unexpected target flag.Akira Hatanaka2011-07-081-1/+2
| | | | llvm-svn: 134671
* Make sure variable Kind is assigned a value to suppress warning.Akira Hatanaka2011-07-081-1/+1
| | | | llvm-svn: 134668
* Define class MipsMCInstLower.Akira Hatanaka2011-07-071-0/+117
llvm-svn: 134633
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