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path: root/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
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* Make helper functions static or move them into anonymous namespaces. NFC.Benjamin Kramer2020-01-141-3/+3
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* [MIPS GlobalISel] Select bitreverse. RecommitPetar Avramovic2019-12-301-0/+4
| | | | | | | | | | | | | | | G_BITREVERSE is generated from llvm.bitreverse.<type> intrinsics, clang genrates these intrinsics from __builtin_bitreverse32 and __builtin_bitreverse64. Add lower and narrowscalar for G_BITREVERSE. Lower G_BITREVERSE on MIPS32. Recommit notes: Introduce temporary variables in order to make sure instructions get inserted into MachineFunction in same order regardless of compiler used to build llvm. Differential Revision: https://reviews.llvm.org/D71363
* Revert "[MIPS GlobalISel] Select bitreverse"Dmitri Gribenko2019-12-301-4/+0
| | | | | | This reverts commit dbc136e0fe7e14c64dcb78e72321bb41af60afa4. It broke buildbots: http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/21066
* [MIPS GlobalISel] Select bitreversePetar Avramovic2019-12-301-0/+4
| | | | | | | | | | G_BITREVERSE is generated from llvm.bitreverse.<type> intrinsics, clang genrates these intrinsics from __builtin_bitreverse32 and __builtin_bitreverse64. Add lower and narrowscalar for G_BITREVERSE. Lower G_BITREVERSE on MIPS32. Differential Revision: https://reviews.llvm.org/D71363
* [MIPS GlobalISel] Select bswapPetar Avramovic2019-12-301-0/+13
| | | | | | | | | G_BSWAP is generated from llvm.bswap.<type> intrinsics, clang genrates these intrinsics from __builtin_bswap32 and __builtin_bswap64. Add lower and narrowscalar for G_BSWAP. Lower G_BSWAP on MIPS32, select G_BSWAP on MIPS32 revision 2 and later. Differential Revision: https://reviews.llvm.org/D71362
* [IR] Split out target specific intrinsic enums into separate headersReid Kleckner2019-12-111-0/+1
| | | | | | | | | | | | | | | | | | | | This has two main effects: - Optimizes debug info size by saving 221.86 MB of obj file size in a Windows optimized+debug build of 'all'. This is 3.03% of 7,332.7MB of object file size. - Incremental step towards decoupling target intrinsics. The enums are still compact, so adding and removing a single target-specific intrinsic will trigger a rebuild of all of LLVM. Assigning distinct target id spaces is potential future work. Part of PR34259 Reviewers: efriedma, echristo, MaskRay Reviewed By: echristo, MaskRay Differential Revision: https://reviews.llvm.org/D71320
* [globalisel] Rename G_GEP to G_PTR_ADDDaniel Sanders2019-11-051-1/+1
| | | | | | | | | | | | | | | | Summary: G_GEP is rather poorly named. It's a simple pointer+scalar addition and doesn't support any of the complexities of getelementptr. I therefore propose that we rename it. There's a G_PTR_MASK so let's follow that convention and go with G_PTR_ADD Reviewers: volkan, aditya_nandakumar, bogner, rovka, arsenm Subscribers: sdardis, jvesely, wdng, nhaehnle, hiraditya, jrtc27, atanasyan, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69734
* [MIPS GlobalISel] Select MSA vector generic and builtin fsqrtPetar Avramovic2019-10-251-4/+16
| | | | | | | | | | | | | selectImpl is able to select G_FSQRT when we set bank for vector operands to fprb. Add detailed tests. Note: G_FSQRT is generated from llvm-ir intrinsics llvm.sqrt.*, and at the moment MIPS is not able to generate this intrinsic for vector type (some targets generate vector llvm.sqrt.* from calls to a builtin function). __builtin_msa_fsqrt_<format> will be transformed into G_FSQRT in legalizeIntrinsic and selected in the same way. Differential Revision: https://reviews.llvm.org/D69376
* [MIPS GlobalISel] Select MSA vector generic and builtin fabsPetar Avramovic2019-10-241-2/+6
| | | | | | | | | | | | | | selectImpl is able to select G_FABS when we set bank for vector operands to fprb. Add detailed tests. Note: G_FABS is generated from llvm-ir intrinsics llvm.fabs.*, and at the moment MIPS is not able to generate this intrinsic for vector type (some targets generate vector llvm.fabs.* from calls to a builtin function). We can handle fabs using __builtin_msa_fmax_a_<format> and passing same vector as both arguments. __builtin_msa_fmax_a_<format> will be directly selected into FMAX_A_<format> in legalizeIntrinsic. Differential Revision: https://reviews.llvm.org/D69346
* [MIPS GlobalISel] MSA vector generic and builtin fadd, fsub, fmul, fdivPetar Avramovic2019-10-241-1/+22
| | | | | | | | | | | Select vector G_FADD, G_FSUB, G_FMUL and G_FDIV for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. __builtin_msa_fadd_<format>, __builtin_msa_fsub_<format>, __builtin_msa_fmul_<format> and __builtin_msa_fdiv_<format> will be transformed into G_FADD, G_FSUB, G_FMUL and G_FDIV in legalizeIntrinsic respectively and selected in the same way. Differential Revision: https://reviews.llvm.org/D69340
* [MIPS GlobalISel] MSA vector generic and builtin sdiv, srem, udiv, uremPetar Avramovic2019-10-241-2/+28
| | | | | | | | | | | Select vector G_SDIV, G_SREM, G_UDIV and G_UREM for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. __builtin_msa_div_s_<format>, __builtin_msa_mod_s_<format>, __builtin_msa_div_u_<format> and __builtin_msa_mod_u_<format> will be transformed into G_SDIV, G_SREM, G_UDIV and G_UREM in legalizeIntrinsic respectively and selected in the same way. Differential Revision: https://reviews.llvm.org/D69333
* [MIPS GlobalISel] Select MSA vector generic and builtin mulPetar Avramovic2019-10-231-5/+6
| | | | | | | | | | Select vector G_MUL for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. Manual selection of G_MUL is now done for gprb only. __builtin_msa_mulv_<format> will be transformed into G_MUL in legalizeIntrinsic and selected in the same way. Differential Revision: https://reviews.llvm.org/D69310
* [MIPS GlobalISel] Select MSA vector generic and builtin subPetar Avramovic2019-10-231-2/+15
| | | | | | | | | | | Select vector G_SUB for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. __builtin_msa_subv_<format> will be transformed into G_SUB in legalizeIntrinsic and selected in the same way. __builtin_msa_subvi_<format> will be directly selected into SUBVI_<format> in legalizeIntrinsic. Differential Revision: https://reviews.llvm.org/D69306
* [MIPS GlobalISel] Select MSA vector generic and builtin addPetar Avramovic2019-10-221-1/+59
| | | | | | | | | | | | | | | Select vector G_ADD for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. __builtin_msa_addv_<format> will be transformed into G_ADD in legalizeIntrinsic and selected in the same way. __builtin_msa_addvi_<format> will be directly selected into ADDVI_<format> in legalizeIntrinsic. MIR tests for it have unnecessary additional copies. Capture current state of tests with run-pass=legalizer with a test in test/CodeGen/MIR/Mips. Differential Revision: https://reviews.llvm.org/D68984 llvm-svn: 375501
* [MIPS GlobalISel] Add MSA registers to fprb. Select vector load, storePetar Avramovic2019-10-151-5/+44
| | | | | | | | | | | | | | | | | | Add vector MSA register classes to fprb, they are 128 bit wide. MSA instructions use the same registers for both integer and floating point operations. Therefore we only need to check for vector element size during legalization or instruction selection. Add helper function in MipsLegalizerInfo and switch to legalIf LegalizeRuleSet to keep legalization rules compact since they depend on MipsSubtarget and presence of MSA. fprb is assigned to all vector operands. Move selectLoadStoreOpCode to MipsInstructionSelector in order to reduce number of arguments. Differential Revision: https://reviews.llvm.org/D68867 llvm-svn: 374872
* [MIPS GlobalISel] VarArg argument lowering, select G_VASTART and vacopyPetar Avramovic2019-09-231-0/+15
| | | | | | | | | | | | | | | | CC_Mips doesn't accept vararg functions for O32, so we have to explicitly use CC_Mips_FixedArg. For lowerCall we now properly figure out whether callee function is vararg or not, this has no effect for O32 since we always use CC_Mips_FixedArg. For lower formal arguments we need to copy arguments in register to stack and save pointer to start for argument list into MipsMachineFunction object so that G_VASTART could use it during instruction select. For vacopy we need to copy content from one vreg to another, load and store are used for that purpose. Differential Revision: https://reviews.llvm.org/D67756 llvm-svn: 372555
* [MIPS GlobalISel] Select indirect branchPetar Avramovic2019-09-121-0/+3
| | | | | | | | Select G_BRINDIRECT for MIPS32. Differential Revision: https://reviews.llvm.org/D67441 llvm-svn: 371730
* [MIPS GlobalISel] Lower G_DYN_STACKALLOCPetar Avramovic2019-09-121-0/+3
| | | | | | | | | | IRTranslator creates G_DYN_STACKALLOC instruction during expansion of alloca when argument that tells number of elements to allocate on stack is a virtual register. Use default lowering for MIPS32. Differential Revision: https://reviews.llvm.org/D67440 llvm-svn: 371728
* [MIPS GlobalISel] Select G_IMPLICIT_DEFPetar Avramovic2019-09-121-0/+3
| | | | | | | | | | G_IMPLICIT_DEF is used for both integer and floating point implicit-def. Handle G_IMPLICIT_DEF as ambiguous opcode in MipsRegisterBankInfo. Select G_IMPLICIT_DEF for MIPS32. Differential Revision: https://reviews.llvm.org/D67439 llvm-svn: 371727
* [MIPS GlobalISel] Select llvm.trap intrinsicPetar Avramovic2019-09-051-1/+14
| | | | | | | | | Select G_INTRINSIC_W_SIDE_EFFECTS for Intrinsic::trap for MIPS32 via legalizeIntrinsic. Differential Revision: https://reviews.llvm.org/D67180 llvm-svn: 371055
* [MIPS GlobalISel] Lower uitofpPetar Avramovic2019-08-301-1/+48
| | | | | | | | Add custom lowering for G_UITOFP for MIPS32. Differential Revision: https://reviews.llvm.org/D66930 llvm-svn: 370432
* [MIPS GlobalISel] Lower fptouiPetar Avramovic2019-08-301-0/+1
| | | | | | | | | | Add lower for G_FPTOUI. Algorithm is similar to the SDAG version in TargetLowering::expandFP_TO_UINT. Lower G_FPTOUI for MIPS32. Differential Revision: https://reviews.llvm.org/D66929 llvm-svn: 370431
* [MIPS GlobalISel] ClampScalar G_SHL, G_ASHR and G_LSHR Petar Avramovic2019-08-271-1/+2
| | | | | | | | ClampScalar G_SHL, G_ASHR and G_LSHR to s32 for MIPS32. Differential Revision: https://reviews.llvm.org/D66533 llvm-svn: 370067
* [MIPS GlobalISel] NarrowScalar G_ZEXTLOAD and G_SEXTLOADPetar Avramovic2019-08-211-3/+3
| | | | | | | | NarrowScalar G_ZEXTLOAD and G_SEXTLOAD to s32 for MIPS32. Differential Revision: https://reviews.llvm.org/D66205 llvm-svn: 369512
* [MIPS GlobalISel] NarrowScalar G_ZEXT and G_SEXTPetar Avramovic2019-08-211-0/+4
| | | | | | | | NarrowScalar G_ZEXT and G_SEXT to s32 for MIPS32. Differential Revision: https://reviews.llvm.org/D66204 llvm-svn: 369511
* [MIPS GlobalISel] Consider type1 when legalizing shifts after r351882Petar Avramovic2019-08-211-2/+2
| | | | | | | | | r351882 allows different type for shift amount then result and value being shifted. Fix MIPS Legalizer rules to take r351882 into account. Differential Revision: https://reviews.llvm.org/D66203 llvm-svn: 369510
* [MIPS GlobalISel] NarrowScalar G_TRUNCPetar Avramovic2019-08-211-0/+4
| | | | | | | | | Add NarrowScalar for G_TRUNC when NarrowTy is half the size of source. NarrowScalar G_TRUNC to s32 for MIPS32. Differential Revision: https://reviews.llvm.org/D66202 llvm-svn: 369509
* [globalisel] Add G_SEXT_INREGDaniel Sanders2019-08-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Targets often have instructions that can sign-extend certain cases faster than the equivalent shift-left/arithmetic-shift-right. Such cases can be identified by matching a shift-left/shift-right pair but there are some issues with this in the context of combines. For example, suppose you can sign-extend 8-bit up to 32-bit with a target extend instruction. %1:_(s32) = G_SHL %0:_(s32), i32 24 # (I've inlined the G_CONSTANT for brevity) %2:_(s32) = G_ASHR %1:_(s32), i32 24 %3:_(s32) = G_ASHR %2:_(s32), i32 1 would reasonably combine to: %1:_(s32) = G_SHL %0:_(s32), i32 24 %2:_(s32) = G_ASHR %1:_(s32), i32 25 which no longer matches the special case. If your shifts and extend are equal cost, this would break even as a pair of shifts but if your shift is more expensive than the extend then it's cheaper as: %2:_(s32) = G_SEXT_INREG %0:_(s32), i32 8 %3:_(s32) = G_ASHR %2:_(s32), i32 1 It's possible to match the shift-pair in ISel and emit an extend and ashr. However, this is far from the only way to break this shift pair and make it hard to match the extends. Another example is that with the right known-zeros, this: %1:_(s32) = G_SHL %0:_(s32), i32 24 %2:_(s32) = G_ASHR %1:_(s32), i32 24 %3:_(s32) = G_MUL %2:_(s32), i32 2 can become: %1:_(s32) = G_SHL %0:_(s32), i32 24 %2:_(s32) = G_ASHR %1:_(s32), i32 23 All upstream targets have been configured to lower it to the current G_SHL,G_ASHR pair but will likely want to make it legal in some cases to handle their faster cases. To follow-up: Provide a way to legalize based on the constant. At the moment, I'm thinking that the best way to achieve this is to provide the MI in LegalityQuery but that opens the door to breaking core principles of the legalizer (legality is not context sensitive). That said, it's worth noting that looking at other instructions and acting on that information doesn't violate this principle in itself. It's only a violation if, at the end of legalization, a pass that checks legality without being able to see the context would say an instruction might not be legal. That's a fairly subtle distinction so to give a concrete example, saying %2 in: %1 = G_CONSTANT 16 %2 = G_SEXT_INREG %0, %1 is legal is in violation of that principle if the legality of %2 depends on %1 being constant and/or being 16. However, legalizing to either: %2 = G_SEXT_INREG %0, 16 or: %1 = G_CONSTANT 16 %2:_(s32) = G_SHL %0, %1 %3:_(s32) = G_ASHR %2, %1 depending on whether %1 is constant and 16 does not violate that principle since both outputs are genuinely legal. Reviewers: bogner, aditya_nandakumar, volkan, aemerson, paquette, arsenm Subscribers: sdardis, jvesely, wdng, nhaehnle, rovka, kristof.beyls, javed.absar, hiraditya, jrtc27, atanasyan, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61289 llvm-svn: 368487
* [MIPS GlobalISel] Select jump_table and brjtPetar Avramovic2019-08-081-1/+4
| | | | | | | | | G_JUMP_TABLE and G_BRJT appear from translation of switch statement. Select these two instructions for MIPS32, both pic and non-pic. Differential Revision: https://reviews.llvm.org/D65861 llvm-svn: 368274
* [MIPS GlobalISel] Select inttoptr and ptrtointPetar Avramovic2019-07-261-1/+4
| | | | | | | | Select G_INTTOPTR and G_PTRTOINT for MIPS32. Differential Revision: https://reviews.llvm.org/D65217 llvm-svn: 367104
* [GlobalISel] Translate calls to memcpy et al to G_INTRINSIC_W_SIDE_EFFECTs ↵Amara Emerson2019-07-191-0/+17
| | | | | | | | | | | | | | and legalize later. I plan on adding memcpy optimizations in the GlobalISel pipeline, but we can't do that unless we delay lowering to actual function calls. This patch changes the translator to generate G_INTRINSIC_W_SIDE_EFFECTS for these functions, and then have each target specify that using the new custom legalizer for intrinsics hook that they want it expanded it a libcall. Differential Revision: https://reviews.llvm.org/D64895 llvm-svn: 366516
* [MIPS GlobalISel] ClampScalar and select pointer G_ICMPPetar Avramovic2019-07-171-1/+2
| | | | | | | | | | | Add narrowScalar to half of original size for G_ICMP. ClampScalar G_ICMP's operands 2 and 3 to to s32. Select G_ICMP for pointers for MIPS32. Pointer compare is same as for integers, it is enough to declare them as legal type. Differential Revision: https://reviews.llvm.org/D64856 llvm-svn: 366317
* [MIPS GlobalISel] Register bank select for G_PHI. Select i64 phiPetar Avramovic2019-07-091-1/+1
| | | | | | | | | | | | | | | Select gprb or fprb when def/use register operand of G_PHI is used/defined by either: copy to/from physical register or instruction with only one mapping available for that use/def operand. Integer s64 phi is handled with narrowScalar when mapping is applied, produced artifacts are combined away. Manually set gprb to all register operands of instructions created during narrowScalar. Differential Revision: https://reviews.llvm.org/D64351 llvm-svn: 365494
* [MIPS GlobalISel] Regbanks for G_SELECT. Select i64, f32 and f64 selectPetar Avramovic2019-07-091-1/+1
| | | | | | | | | | | | | | | | | | Select gprb or fprb when def/use register operand of G_SELECT is used/defined by either: copy to/from physical register or instruction with only one mapping available for that use/def operand. Integer s64 select is handled with narrowScalar when mapping is applied, produced artifacts are combined away. Manually set gprb to all register operands of instructions created during narrowScalar. For selection of floating point s32 or s64 select it is enough to set fprb of appropriate size and selectImpl will do the rest. Differential Revision: https://reviews.llvm.org/D64350 llvm-svn: 365492
* [MIPS GlobalISel] Register bank select for G_LOAD. Select i64 loadPetar Avramovic2019-07-081-0/+3
| | | | | | | | | | | | | | Select gprb or fprb when loaded value is used by either: copy to physical register or instruction with only one mapping available for that use operand. Load of integer s64 is handled with narrowScalar when mapping is applied, produced artifacts are combined away. Manually set gprb to all register operands of instructions created during narrowScalar. Differential Revision: https://reviews.llvm.org/D64269 llvm-svn: 365323
* [MIPS GlobalISel] Register bank select for G_STORE. Select i64 storePetar Avramovic2019-07-081-0/+4
| | | | | | | | | | | | | | Select gprb or fprb when stored value is defined by either: copy from physical register or instruction with only one mapping available for that def operand. Store of integer s64 is handled with narrowScalar when mapping is applied, produced artifacts are combined away. Manually set gprb to all register operands of instructions created during narrowScalar. Differential Revision: https://reviews.llvm.org/D64268 llvm-svn: 365322
* [MIPS GlobalISel] Select integer to floating point conversionsPetar Avramovic2019-06-201-0/+10
| | | | | | | | Select G_SITOFP and G_UITOFP for MIPS32. Differential Revision: https://reviews.llvm.org/D63542 llvm-svn: 363912
* [MIPS GlobalISel] Select floating point to integer conversionsPetar Avramovic2019-06-201-0/+10
| | | | | | | | Select G_FPTOSI and G_FPTOUI for MIPS32. Differential Revision: https://reviews.llvm.org/D63541 llvm-svn: 363911
* [MIPS GlobalISel] Select sqrtPetar Avramovic2019-06-061-1/+1
| | | | | | | | Select G_FSQRT for MIPS32. Differential Revision: https://reviews.llvm.org/D62905 llvm-svn: 362692
* [MIPS GlobalISel] Select fabsPetar Avramovic2019-06-061-1/+1
| | | | | | | | Select G_FABS for MIPS32. Differential Revision: https://reviews.llvm.org/D62903 llvm-svn: 362690
* [MIPS GlobalISel] Select fpext and fptruncPetar Avramovic2019-06-061-0/+6
| | | | | | | | Select G_FPEXT and G_FPTRUNC for MIPS32. Differential Revision: https://reviews.llvm.org/D62902 llvm-svn: 362689
* [MIPS GlobalISel] Select floor and ceilPetar Avramovic2019-06-061-0/+3
| | | | | | | | Select G_FFLOOR and G_FCEIL for MIPS32. Differential Revision: https://reviews.llvm.org/D62901 llvm-svn: 362688
* [MIPS GlobalISel] Select fcmpPetar Avramovic2019-06-051-0/+4
| | | | | | | | Select floating point compare for MIPS32. Differential Revision: https://reviews.llvm.org/D62721 llvm-svn: 362603
* [MIPS GlobalISel] Select floating point arithmetic operationsPetar Avramovic2019-04-031-3/+7
| | | | | | | | Select 32 and 64 bit floating point add, sub, mul and div for MIPS32. Differential Revision: https://reviews.llvm.org/D60191 llvm-svn: 357584
* [MIPS GlobalISel] Select float constantsPetar Avramovic2019-03-281-0/+3
| | | | | | | | Select 32 and 64 bit float constants for MIPS32. Differential Revision: https://reviews.llvm.org/D59933 llvm-svn: 357183
* [MIPS GlobalISel] NarrowScalar G_UMULHPetar Avramovic2019-03-111-1/+2
| | | | | | | | | | NarrowScalar G_UMULH in LegalizerHelper using multiplyRegisters helper function. NarrowScalar G_UMULH for MIPS32. Differential Revision: https://reviews.llvm.org/D58825 llvm-svn: 355815
* [MIPS GlobalISel] NarrowScalar G_MULPetar Avramovic2019-03-111-5/+1
| | | | | | | | | | | | | Narrow Scalar G_MUL for MIPS32. Revisit NarrowScalar implementation in LegalizerHelper. Introduce new helper function multiplyRegisters. It performs generic multiplication of values held in multiple registers. Generated instructions use only types NarrowTy and i1. Destination can be same or two times size of the source. Differential Revision: https://reviews.llvm.org/D58824 llvm-svn: 355814
* [MIPS GlobalISel] Select G_UMULHPetar Avramovic2019-03-011-1/+4
| | | | | | | | Legalize G_UMULO and select G_UMULH for MIPS32. Differential Revision: https://reviews.llvm.org/D58714 llvm-svn: 355177
* [MIPS GlobalISel] Select G_UADDOPetar Avramovic2019-02-261-1/+1
| | | | | | | | | Lower G_UADDO. Legalize G_UADDO for MIPS32 Differential Revision: https://reviews.llvm.org/D58671 llvm-svn: 354900
* GlobalISel: Add alignment to LegalityQuery MMOsMatt Arsenault2019-02-141-6/+6
| | | | | | | This allows targets to specify the minimum alignment required for the load/store. llvm-svn: 354071
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