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* Add an option to use a virtual register as the global base register instead ofAkira Hatanaka2012-02-241-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... llvm-svn: 151402
* Emit B (unconditional branch) when -relocation-model=pic and J (jump) whenAkira Hatanaka2011-12-121-0/+1
| | | | | | -relocation-model=static. llvm-svn: 146432
* Mips MC object code emission improvements:Bruno Cardoso Lopes2011-11-111-80/+0
| | | | | | | | | | "With this patch we can now generate runnable Mips code through LLVM direct object emission. We have run numerous simple programs, both C and C++ and with -O0 and -O3 from the output. The code is not production ready, but quite useful for experimentation." Patch and message by Jack Carter llvm-svn: 144414
* Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot.Akira Hatanaka2011-10-111-0/+1
| | | | llvm-svn: 141613
* Add enums and functions for symbols Mips64 uses.Akira Hatanaka2011-09-221-1/+8
| | | | llvm-svn: 140295
* One more patch towards JIT support for Mips.Bruno Cardoso Lopes2011-09-141-0/+27
| | | | | | | | | | | | | | - Add TSFlags for the instruction formats. The idea here is to use as much encoding as possible from getBinaryCodeForInstr, and having TSFLags formats for that would make it easier to encode most part of the instructions (since Mips encodings are pretty straightforward) - Improve the mips mechanism for compilation callback - Add Mips specific code for invalidating the instruction cache - Next patch will address wrong tablegen encoding Commit msg added by my own but the patch is from Sasa Stankovic. llvm-svn: 139688
* Lower MachineInstr to MC Inst and print to .s files. Akira Hatanaka2011-07-071-92/+1
| | | | llvm-svn: 134661
* Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng2011-07-011-1/+4
| | | | llvm-svn: 134244
* Improve Mips back-end's handling of DBG_VALUE. Akira Hatanaka2011-07-011-0/+5
| | | | llvm-svn: 134224
* This patch implements the thread local storage. Implemented are GeneralBruno Cardoso Lopes2011-05-311-1/+15
| | | | | | | | Dynamic, Initial Exec and Local Exec TLS models. Patch by Sasa Stankovic llvm-svn: 132322
* Reverse unnecessary changes made in r129606 and r129608. There is no change ↵Akira Hatanaka2011-04-151-6/+5
| | | | | | in functionality. llvm-svn: 129612
* Fix lines that have incorrect indentation or exceed 80 columns. There is no ↵Akira Hatanaka2011-04-151-5/+6
| | | | | | change in functionality. llvm-svn: 129606
* Simplifies logic for printing target flags.Akira Hatanaka2011-04-011-3/+3
| | | | llvm-svn: 128741
* Add code for analyzing FP branches. Clean up branch Analysis functions.Akira Hatanaka2011-04-011-16/+10
| | | | llvm-svn: 128718
* Added support for FP conditional move instructions and fixed bugs in ↵Akira Hatanaka2011-03-311-9/+9
| | | | | | handling of FP comparisons. llvm-svn: 128650
* Remove (hopefully) all trailing whitespaces from the mips backend. Patch by ↵Bruno Cardoso Lopes2011-03-041-11/+11
| | | | | | Hatanaka, Akira llvm-svn: 127003
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-161-6/+0
| | | | llvm-svn: 108567
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-111-12/+0
| | | | | | | | The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. llvm-svn: 108099
* Replace copyRegToReg with copyPhysReg for Mips.Jakob Stoklund Olesen2010-07-111-6/+4
| | | | llvm-svn: 108066
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-171-1/+2
| | | | | | | | | | | | addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-1/+2
| | | | | | doesn't have to guess. llvm-svn: 103194
* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-061-2/+4
| | | | llvm-svn: 103193
* Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor ofDan Gohman2009-12-051-1/+0
| | | | | | | MachineBasicBlock::canFallThrough(), which is target-independent and more thorough. llvm-svn: 90634
* Remove explicit enum integer values. They don't appear to be needed, andDan Gohman2009-10-051-5/+5
| | | | | | they make it less convenient to add new entries. llvm-svn: 83308
* Reapply 80278Bruno Cardoso Lopes2009-09-011-0/+32
| | | | | | | | Add MO flags to simplify the printing of relocations. Remove the support for printing large code model relocs (which aren't supported anyway). llvm-svn: 80691
* Revert 80278 for now, it caused a lot of MIPS tests to failBruno Cardoso Lopes2009-08-271-32/+0
| | | | llvm-svn: 80280
* Revamp our friend Mips :)Bruno Cardoso Lopes2009-08-271-0/+32
| | | | | | | | Add MO flags to simplify the printing of relocations. Remove the support for printing large code model relocs (which aren't supported anyway). llvm-svn: 80278
* Remove unused member functions.Eli Friedman2009-07-241-10/+0
| | | | llvm-svn: 76960
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-1/+1
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* assert(0) -> LLVM_UNREACHABLE.Torok Edwin2009-07-111-1/+2
| | | | | | | | | Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
* Convert Alpha and Mips to use a MachineFunctionInfo subclass toDan Gohman2009-06-031-0/+6
| | | | | | | | | | carry GlobalBaseReg, and GlobalRetAddr too in Alpha's case. This eliminates the need for them to search through the MachineRegisterInfo livein list in order to identify these virtual registers. EmitLiveInCopies is now the only user of the virtual register portion of MachineRegisterInfo's livein data. llvm-svn: 72802
* Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nastyEvan Cheng2009-02-091-1/+2
| | | | | | | | suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. llvm-svn: 64124
* Change TargetInstrInfo::isMoveInstr to return source and destination ↵Evan Cheng2009-01-201-4/+4
| | | | | | sub-register indices as well. llvm-svn: 62600
* Split foldMemoryOperand into public non-virtual and protected virtualDan Gohman2008-12-031-9/+9
| | | | | | | parts, and add target-independent code to add/preserve MachineMemOperands. llvm-svn: 60488
* Add more const qualifiers. This fixes build breakage from r59540.Dan Gohman2008-11-181-2/+4
| | | | llvm-svn: 59542
* Const-ify several TargetInstrInfo methods.Dan Gohman2008-10-161-3/+3
| | | | llvm-svn: 57622
* Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy ↵Owen Anderson2008-08-261-1/+1
| | | | | | | | | requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
* Convert uses of std::vector in TargetInstrInfo to SmallVector. This change ↵Owen Anderson2008-08-141-3/+4
| | | | | | had to be propoagated down into all the targets and up into all clients of this API. llvm-svn: 54802
* Added floating point lowering for setcc and brcond.Bruno Cardoso Lopes2008-07-281-1/+10
| | | | | | | Fixed COMM asm directive usage. ConstantPool using custom FourByteConstantSection. llvm-svn: 54139
* Fixe typos and 80 column size problemsBruno Cardoso Lopes2008-07-091-1/+2
| | | | llvm-svn: 53272
* Several changes to Mips backend, experimental fp support being the mostBruno Cardoso Lopes2008-07-051-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
* Change target-specific classes to use more precise static types.Dan Gohman2008-05-141-1/+1
| | | | | | | This eliminates the need for several awkward casts, including the last dynamic_cast under lib/Target. llvm-svn: 51091
* Add explicit keywords.Dan Gohman2008-03-251-1/+1
| | | | llvm-svn: 48801
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-1/+1
| | | | llvm-svn: 46930
* It's not always safe to fold movsd into xorpd, etc. Check the alignment of ↵Evan Cheng2008-02-081-2/+4
| | | | | | the load address first to make sure it's 16 byte aligned. llvm-svn: 46893
* Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson2008-01-071-0/+11
| | | | | | Some day I'll get it all moved over... llvm-svn: 45672
* Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson2008-01-011-0/+19
| | | | llvm-svn: 45484
* Fix a problem where lib/Target/TargetInstrInfo.h would include and useChris Lattner2008-01-011-2/+1
| | | | | | | | | | a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. llvm-svn: 45475
* Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson2007-12-311-0/+4
| | | | | | Machine-level API cleanup instigated by Chris. llvm-svn: 45470
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
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