bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Fixe typos and 80 column size problems	Bruno Cardoso Lopes	2008-07-09	1	-1/+2
\| \| \| \|	llvm-svn: 53272
*	Several changes to Mips backend, experimental fp support being the most	Bruno Cardoso Lopes	2008-07-05	1	-0/+78
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - Added Float Point Instructions, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
*	Change target-specific classes to use more precise static types.	Dan Gohman	2008-05-14	1	-1/+1
\| \| \| \| \| \| \|	This eliminates the need for several awkward casts, including the last dynamic_cast under lib/Target. llvm-svn: 51091
*	Add explicit keywords.	Dan Gohman	2008-03-25	1	-1/+1
\| \| \| \|	llvm-svn: 48801
*	Rename MRegisterInfo to TargetRegisterInfo.	Dan Gohman	2008-02-10	1	-1/+1
\| \| \| \|	llvm-svn: 46930
*	It's not always safe to fold movsd into xorpd, etc. Check the alignment of ↵	Evan Cheng	2008-02-08	1	-2/+4
\| \| \| \| \| \|	the load address first to make sure it's 16 byte aligned. llvm-svn: 46893
*	Move even more functionality from MRegisterInfo into TargetInstrInfo.	Owen Anderson	2008-01-07	1	-0/+11
\| \| \| \| \| \|	Some day I'll get it all moved over... llvm-svn: 45672
*	Move some more instruction creation methods from RegisterInfo into InstrInfo.	Owen Anderson	2008-01-01	1	-0/+19
\| \| \| \|	llvm-svn: 45484
*	Fix a problem where lib/Target/TargetInstrInfo.h would include and use	Chris Lattner	2008-01-01	1	-2/+1
\| \| \| \| \| \| \| \| \| \|	a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. llvm-svn: 45475
*	Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the	Owen Anderson	2007-12-31	1	-0/+4
\| \| \| \| \| \|	Machine-level API cleanup instigated by Chris. llvm-svn: 45470
*	Remove attribution from file headers, per discussion on llvmdev.	Chris Lattner	2007-12-29	1	-2/+2
\| \| \| \|	llvm-svn: 45418
*	Mask directive completed with CalleeSave info	Bruno Cardoso Lopes	2007-08-28	1	-2/+1
\| \| \| \| \| \|	Comments for Mips directives added. llvm-svn: 41526
*	Branch Analysis and InsertNoop inserted into header files	Bruno Cardoso Lopes	2007-08-18	1	-2/+36
\| \| \| \|	llvm-svn: 41155
*	Initial Mips support, here we go! =)	Bruno Cardoso Lopes	2007-06-06	1	-0/+63
	- Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. llvm-svn: 37461