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* Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integerAkira Hatanaka2011-10-031-51/+44
| | | | | | registers. llvm-svn: 141019
* Revert r140731, "Define classes for unary and binary FP instructions and use ↵Jakob Stoklund Olesen2011-09-281-1/+1
| | | | | | | | them to define" It broke the unit tests. Please reapply with tests fixed. llvm-svn: 140735
* Define classes for unary and binary FP instructions and use them to defineAkira Hatanaka2011-09-281-1/+1
| | | | | | multiclasses. llvm-svn: 140731
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Fix handling of double precision loads and stores when Mips1 is targeted. Akira Hatanaka2011-08-161-26/+4
| | | | | | | | | | | | | | | Mips1 does not support double precision loads or stores, therefore two single precision loads or stores must be used in place of these instructions. This patch treats double precision loads and stores as if they are legal instructions until MCInstLowering, instead of generating the single precision instructions during instruction selection or Prolog/Epilog code insertion. Without the changes made in this patch, llc produces code that has the same problem described in r137484 or bails out when MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before register allocation. llvm-svn: 137711
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-11/+0
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-1/+12
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Lower MachineInstr to MC Inst and print to .s files. Akira Hatanaka2011-07-071-0/+6
| | | | llvm-svn: 134661
* Reverse order of operands of address operand mem so that the base operand comesAkira Hatanaka2011-07-071-18/+18
| | | | | | | before the offset. This change will enable simplification of function MipsRegisterInfo::eliminateFrameIndex. llvm-svn: 134625
* Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng2011-07-011-2/+2
| | | | llvm-svn: 134244
* Improve Mips back-end's handling of DBG_VALUE. Akira Hatanaka2011-07-011-0/+9
| | | | llvm-svn: 134224
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-281-1/+2
| | | | llvm-svn: 134030
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-0/+2
| | | | llvm-svn: 134024
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-2/+2
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Reverse unnecessary changes made in r129606 and r129608. There is no change ↵Akira Hatanaka2011-04-151-10/+9
| | | | | | in functionality. llvm-svn: 129612
* Fix lines that have incorrect indentation or exceed 80 columns. There is no ↵Akira Hatanaka2011-04-151-9/+10
| | | | | | change in functionality. llvm-svn: 129606
* Add code for analyzing FP branches. Clean up branch Analysis functions.Akira Hatanaka2011-04-011-207/+128
| | | | llvm-svn: 128718
* Added support for FP conditional move instructions and fixed bugs in ↵Akira Hatanaka2011-03-311-5/+5
| | | | | | handling of FP comparisons. llvm-svn: 128650
* Remove (hopefully) all trailing whitespaces from the mips backend. Patch by ↵Bruno Cardoso Lopes2011-03-041-37/+37
| | | | | | Hatanaka, Akira llvm-svn: 127003
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-161-47/+0
| | | | llvm-svn: 108567
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-111-74/+0
| | | | | | | | The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. llvm-svn: 108099
* Replace copyRegToReg with copyPhysReg for Mips.Jakob Stoklund Olesen2010-07-111-50/+64
| | | | llvm-svn: 108066
* Use COPY in targetsJakob Stoklund Olesen2010-07-101-6/+2
| | | | llvm-svn: 108063
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-171-9/+8
| | | | | | | | | | | | addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-5/+4
| | | | | | doesn't have to guess. llvm-svn: 103194
* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-061-2/+4
| | | | llvm-svn: 103193
* No-ops emitted for scheduling don't correspond with anything in theDan Gohman2010-05-051-1/+0
| | | | | | user's source, so don't arbitrarily assign them a debug location. llvm-svn: 103121
* use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()Chris Lattner2010-04-021-5/+5
| | | | llvm-svn: 100214
* Teach AnalyzeBranch, RemoveBranch and the branchDale Johannesen2010-04-021-1/+14
| | | | | | | folder to be tolerant of debug info following the branch(es) at the end of a block. llvm-svn: 100168
* load f64 +0.0 in a cleaner way. This fix part of PR5445Bruno Cardoso Lopes2010-01-191-9/+0
| | | | llvm-svn: 93876
* Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor ofDan Gohman2009-12-051-16/+0
| | | | | | | MachineBasicBlock::canFallThrough(), which is target-independent and more thorough. llvm-svn: 90634
* Add proper emission of load/store double to stack slots for mips1 targets!Bruno Cardoso Lopes2009-11-251-21/+43
| | | | llvm-svn: 89821
* Support fp64 immediate zero, this fixes only part of PR5445 Bruno Cardoso Lopes2009-11-131-3/+12
| | | | | | because the testcase is triggering one more bug. llvm-svn: 88674
* Remove unused member functions.Eli Friedman2009-07-241-45/+0
| | | | llvm-svn: 76960
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-2/+2
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* assert(0) -> LLVM_UNREACHABLE.Torok Edwin2009-07-111-2/+3
| | | | | | | | | Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
* Silence a warning when assertions are turned off.Duncan Sands2009-07-031-0/+1
| | | | llvm-svn: 74779
* Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves ↵Evan Cheng2009-07-011-4/+10
| | | | | | the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. llvm-svn: 74580
* Convert Alpha and Mips to use a MachineFunctionInfo subclass toDan Gohman2009-06-031-0/+29
| | | | | | | | | | carry GlobalBaseReg, and GlobalRetAddr too in Alpha's case. This eliminates the need for them to search through the MachineRegisterInfo livein list in order to identify these virtual registers. EmitLiveInCopies is now the only user of the virtual register portion of MachineRegisterInfo's livein data. llvm-svn: 72802
* Added support for fround, fextend and FP_TO_SINTBruno Cardoso Lopes2009-05-271-10/+15
| | | | llvm-svn: 72483
* Change MachineInstrBuilder::addReg() to take a flag instead of a list ofBill Wendling2009-05-131-6/+6
| | | | | | | | | | | | booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
* fix some warnings in release-asserts mode.Chris Lattner2009-03-261-20/+19
| | | | llvm-svn: 67738
* Removed AFGR32 register classBruno Cardoso Lopes2009-03-211-34/+18
| | | | | | Handle odd registers allocation in FGR32. llvm-svn: 67422
* Factor out the code to add a MachineOperand to a MachineInstrBuilder.Dan Gohman2009-02-181-18/+4
| | | | llvm-svn: 64891
* Remove non-DebugLoc versions of BuildMI from IA64, Mips.Dale Johannesen2009-02-131-6/+8
| | | | llvm-svn: 64438
* Eliminate a couple of non-DebugLoc BuildMI variants.Dale Johannesen2009-02-121-2/+4
| | | | | | Modify callers. llvm-svn: 64409
* Move debug loc info along when the spiller creates new instructions.Bill Wendling2009-02-121-22/+35
| | | | llvm-svn: 64342
* Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nastyEvan Cheng2009-02-091-2/+4
| | | | | | | | suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. llvm-svn: 64124
* Change TargetInstrInfo::isMoveInstr to return source and destination ↵Evan Cheng2009-01-201-1/+4
| | | | | | sub-register indices as well. llvm-svn: 62600
* Split foldMemoryOperand into public non-virtual and protected virtualDan Gohman2008-12-031-4/+4
| | | | | | | parts, and add target-independent code to add/preserve MachineMemOperands. llvm-svn: 60488
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