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path: root/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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* mips16: When copying operands in a conditional branch instruction, allow forAkira Hatanaka2012-09-131-3/+9
| | | | | | | | immediate operands to be copied. Patch by Reed Kotler. llvm-svn: 163811
* Make function loadImmediate a member of MipsSEInstrInfo and change it to returnAkira Hatanaka2012-08-231-43/+0
| | | | | | | | | | the temporary register that was used to load the immediate. Currently, it always returns register $at, but this will change if, in the future, we decide to use another register. No changes in functionality. llvm-svn: 162417
* Move the code that creates instances of MipsInstrInfo and MipsFrameLowering outAkira Hatanaka2012-08-021-0/+7
| | | | | | of MipsTargetMachine.cpp. llvm-svn: 161191
* Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo andAkira Hatanaka2012-07-311-5/+1
| | | | | | MipsSERegisterInfo. llvm-svn: 161092
* Add definitions of two subclasses of MipsInstrInfo, MipsInstrInfo (for mips16),Akira Hatanaka2012-07-311-293/+9
| | | | | | and MipsSEInstrInfo (for mips32/64). llvm-svn: 161081
* Add basic ability to setup call frame, and make procedure calls.Akira Hatanaka2012-07-231-3/+15
| | | | | | | | Hello world will compile and execute with this patch. Patch by Reed Kotler. llvm-svn: 160651
* Revert accidental commit.Akira Hatanaka2012-07-211-15/+3
| | | | llvm-svn: 160598
* Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind.Akira Hatanaka2012-07-211-3/+15
| | | | | | Test case will be added later when long branch patch is checked in. llvm-svn: 160597
* Make register Mips::RA allocatable if not in mips16 mode.Akira Hatanaka2012-07-101-0/+13
| | | | llvm-svn: 159971
* Fix coding style violations. Remove white spaces and tabs.Akira Hatanaka2012-06-141-2/+2
| | | | llvm-svn: 158471
* Define function MipsInstrInfo::GetInstSizeInBytes, which will be called toAkira Hatanaka2012-06-141-0/+56
| | | | | | | compute the size of basic blocks in a function. Also, define a function which emits a series of instructions to load an immediate. llvm-svn: 158429
* Fix some uses of getSubRegisters() to use getSubReg() instead.Jakob Stoklund Olesen2012-05-301-6/+10
| | | | | | | It is better to address sub-registers directly by name instead of relying on their position in the sub-register list. llvm-svn: 157703
* Move the code in MipsExpandPseudo to MipsInstrInfo::expandPostRAPseudo.Akira Hatanaka2012-05-251-0/+47
| | | | | | Delete MipsExpandPseudo. llvm-svn: 157495
* This patch adds the register class for MIPS16 as well as the ability forAkira Hatanaka2012-05-161-10/+10
| | | | | | | | | | | | | | | llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the mips16 ASE for mips32 by default. As part of fixing of adding this we discovered some small changes that need to be made to MipsInstrInfo::storeRegToStackSLot and MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead, per suggestion of Jakob Stoklund Olesen. Patch by Reed Kotler. llvm-svn: 156958
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-10/+10
| | | | | | since they are equivalent. llvm-svn: 155188
* remove blanks, and some code formatJia Liu2012-02-281-6/+6
| | | | llvm-svn: 151625
* Add an option to use a virtual register as the global base register instead ofAkira Hatanaka2012-02-241-27/+0
| | | | | | | | | | | | | | | | | | | | | | | | | reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... llvm-svn: 151402
* remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.Jia Liu2012-02-171-1/+1
| | | | llvm-svn: 150805
* Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which isAkira Hatanaka2012-02-031-3/+6
| | | | | | | | needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. llvm-svn: 149668
* Add MachineMemOperands to instructions generated in storeRegToStackSlot orAkira Hatanaka2011-12-241-2/+16
| | | | | | loadRegFromStackSlot. llvm-svn: 147235
* Tidy up. Simplify logic. No functional change intended.Akira Hatanaka2011-12-191-15/+15
| | | | llvm-svn: 146896
* Emit B (unconditional branch) when -relocation-model=pic and J (jump) whenAkira Hatanaka2011-12-121-8/+9
| | | | | | -relocation-model=static. llvm-svn: 146432
* Use branches instead of jumps + variable cleanup. Testcase coming next. ↵Bruno Cardoso Lopes2011-12-061-6/+6
| | | | | | Patch by Jack Carter llvm-svn: 145912
* Add code needed for copying between 64-bit integer and floating pointerAkira Hatanaka2011-11-071-0/+6
| | | | | | registers. llvm-svn: 144017
* Add support for conditional branch instructions with 64-bit register operands.Akira Hatanaka2011-10-111-11/+20
| | | | llvm-svn: 141694
* Make changes necessary for supporting floating point load and store instructionsAkira Hatanaka2011-10-111-6/+18
| | | | | | | that have 64-bit pointers or access the 32 x 64-bit floating pointer register file. Update functions in MipsInstrInfo.cpp too. llvm-svn: 141623
* Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot.Akira Hatanaka2011-10-111-17/+23
| | | | llvm-svn: 141613
* Simplify definition of FP move instructions.Akira Hatanaka2011-10-081-1/+1
| | | | llvm-svn: 141476
* Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integerAkira Hatanaka2011-10-031-51/+44
| | | | | | registers. llvm-svn: 141019
* Revert r140731, "Define classes for unary and binary FP instructions and use ↵Jakob Stoklund Olesen2011-09-281-1/+1
| | | | | | | | them to define" It broke the unit tests. Please reapply with tests fixed. llvm-svn: 140735
* Define classes for unary and binary FP instructions and use them to defineAkira Hatanaka2011-09-281-1/+1
| | | | | | multiclasses. llvm-svn: 140731
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Fix handling of double precision loads and stores when Mips1 is targeted. Akira Hatanaka2011-08-161-26/+4
| | | | | | | | | | | | | | | Mips1 does not support double precision loads or stores, therefore two single precision loads or stores must be used in place of these instructions. This patch treats double precision loads and stores as if they are legal instructions until MCInstLowering, instead of generating the single precision instructions during instruction selection or Prolog/Epilog code insertion. Without the changes made in this patch, llc produces code that has the same problem described in r137484 or bails out when MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before register allocation. llvm-svn: 137711
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-11/+0
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-1/+12
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Lower MachineInstr to MC Inst and print to .s files. Akira Hatanaka2011-07-071-0/+6
| | | | llvm-svn: 134661
* Reverse order of operands of address operand mem so that the base operand comesAkira Hatanaka2011-07-071-18/+18
| | | | | | | before the offset. This change will enable simplification of function MipsRegisterInfo::eliminateFrameIndex. llvm-svn: 134625
* Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng2011-07-011-2/+2
| | | | llvm-svn: 134244
* Improve Mips back-end's handling of DBG_VALUE. Akira Hatanaka2011-07-011-0/+9
| | | | llvm-svn: 134224
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-281-1/+2
| | | | llvm-svn: 134030
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-0/+2
| | | | llvm-svn: 134024
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-2/+2
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Reverse unnecessary changes made in r129606 and r129608. There is no change ↵Akira Hatanaka2011-04-151-10/+9
| | | | | | in functionality. llvm-svn: 129612
* Fix lines that have incorrect indentation or exceed 80 columns. There is no ↵Akira Hatanaka2011-04-151-9/+10
| | | | | | change in functionality. llvm-svn: 129606
* Add code for analyzing FP branches. Clean up branch Analysis functions.Akira Hatanaka2011-04-011-207/+128
| | | | llvm-svn: 128718
* Added support for FP conditional move instructions and fixed bugs in ↵Akira Hatanaka2011-03-311-5/+5
| | | | | | handling of FP comparisons. llvm-svn: 128650
* Remove (hopefully) all trailing whitespaces from the mips backend. Patch by ↵Bruno Cardoso Lopes2011-03-041-37/+37
| | | | | | Hatanaka, Akira llvm-svn: 127003
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-161-47/+0
| | | | llvm-svn: 108567
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-111-74/+0
| | | | | | | | The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. llvm-svn: 108099
* Replace copyRegToReg with copyPhysReg for Mips.Jakob Stoklund Olesen2010-07-111-50/+64
| | | | llvm-svn: 108066
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