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* MIPS DSP: add support for extract-word instructions.Akira Hatanaka2012-09-271-0/+2
| | | | llvm-svn: 164749
* Add MIPS DSP register classes. Set actions of DSP vector operations and overrideAkira Hatanaka2012-09-211-0/+10
| | | | | | TargetLowering's callback functions. llvm-svn: 164431
* SelectionDAG node enums for MIPS DSP nodes.Akira Hatanaka2012-09-211-0/+41
| | | | llvm-svn: 164430
* Expand DYNAMIC_STACKALLOC nodes rather than doing custom-lowering.Akira Hatanaka2012-07-311-1/+0
| | | | | | | The frame object which points to the dynamically allocated area will not be needed after changes are made to cease reserving call frames. llvm-svn: 161076
* Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC.Akira Hatanaka2012-07-111-0/+1
| | | | llvm-svn: 160064
* Lower RETURNADDR node in Mips backend.Akira Hatanaka2012-07-111-0/+1
| | | | | | Patch by Sasa Stankovic. llvm-svn: 160031
* Fix coding style violations. Remove white spaces and tabs.Akira Hatanaka2012-06-141-1/+2
| | | | llvm-svn: 158471
* Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp.Akira Hatanaka2012-06-131-0/+5
| | | | llvm-svn: 158414
* Define functions MipsTargetLowering::LowerLOAD and LowerSTORE whichAkira Hatanaka2012-06-021-0/+2
| | | | | | custom-lower unaligned load and store nodes. llvm-svn: 157864
* Define Mips specific unaligned load/store nodes.Akira Hatanaka2012-06-021-1/+11
| | | | llvm-svn: 157863
* Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCallJustin Holewinski2012-05-251-7/+1
| | | | | | | | | | to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB llvm-svn: 157479
* Expand 64-bit shifts if target ABI is O32.Akira Hatanaka2012-05-091-0/+2
| | | | llvm-svn: 156457
* Add support for the 'I' inline asm constraint. Also add testsEric Christopher2012-05-071-0/+9
| | | | | | | | from the previous 2 patches. Patch by Jack Carter. llvm-svn: 156279
* Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user.Akira Hatanaka2012-04-111-0/+1
| | | | | | Invalid operation is signaled if the operand of these instructions is NaN. llvm-svn: 154545
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-2/+2
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* Lower SETCC nodes during legalization. Previously, it was lowered in DAG ↵Akira Hatanaka2012-03-091-0/+1
| | | | | | combine pass. llvm-svn: 152450
* Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng2012-02-281-1/+1
| | | | | | direct call. llvm-svn: 151645
* Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar2012-02-281-1/+1
| | | | | | prediction. ...", it is breaking the Clang build during the Compiler-RT part. llvm-svn: 151630
* remove blanks, and some code formatJia Liu2012-02-281-1/+1
| | | | llvm-svn: 151625
* Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2012-02-281-1/+1
| | | | | | | | | | | | | | | | | the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 llvm-svn: 151623
* Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which isAkira Hatanaka2012-02-031-0/+2
| | | | | | | | needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. llvm-svn: 149668
* Rename WrapperPIC. It is now used for both pic and static.Akira Hatanaka2011-12-091-1/+1
| | | | llvm-svn: 146232
* Implement 64-bit support for thread local storage handling.Akira Hatanaka2011-12-081-7/+0
| | | | | | | | | | - Modify lowering of global TLS address nodes. - Modify isel of ThreadPointer. - Wrap target global TLS address nodes that are operands of loads with WrapperPIC. - Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be substituted with other existing nodes. llvm-svn: 146175
* Make the type of shift amount i32 in order to reduce the number of shiftAkira Hatanaka2011-11-071-0/+2
| | | | | | instruction definitions. llvm-svn: 143989
* Add variable IsO32 to MipsTargetLowering.Akira Hatanaka2011-10-281-1/+1
| | | | llvm-svn: 143213
* Modify lowering of GlobalAddress so that correct code is emitted when target isAkira Hatanaka2011-10-111-1/+1
| | | | | | Mips64. llvm-svn: 141618
* Define variable HasMips64 in MipsTargetLowering.Akira Hatanaka2011-09-261-1/+2
| | | | llvm-svn: 140569
* Add codegen support for vector select (in the IR this means a selectDuncan Sands2011-09-061-1/+1
| | | | | | | | | | | | with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. llvm-svn: 139159
* Move pattern matching for EXT and INS to post-legalization DAGCombine per ↵Akira Hatanaka2011-08-171-2/+0
| | | | | | Bruno's comment. llvm-svn: 137831
* Add support for ext and ins.Akira Hatanaka2011-08-171-1/+6
| | | | llvm-svn: 137804
* Define unaligned load and store. Akira Hatanaka2011-08-121-0/+2
| | | | llvm-svn: 137515
* Code generation for 'fence' instruction.Eli Friedman2011-07-271-0/+1
| | | | llvm-svn: 136283
* Lower memory barriers to sync instructions.Akira Hatanaka2011-07-191-1/+4
| | | | llvm-svn: 135537
* Remove getRegClassForInlineAsmConstraint for Mips.Eric Christopher2011-06-291-4/+0
| | | | | | Part of rdar://9643582 llvm-svn: 134084
* Re-apply 132758 and 132768 which were speculatively reverted in 132777. Akira Hatanaka2011-06-211-1/+3
| | | | llvm-svn: 133494
* Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.Eric Christopher2011-06-091-3/+1
| | | | llvm-svn: 132777
* Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of theAkira Hatanaka2011-06-081-1/+3
| | | | | | dynamically allocated stack area was not set. llvm-svn: 132758
* Custom-lower FRAMEADDR. Patch by Sasa Stankovic.Akira Hatanaka2011-06-021-0/+1
| | | | llvm-svn: 132444
* This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor,Bruno Cardoso Lopes2011-05-311-0/+10
| | | | | | | | | | nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
* This patch implements the thread local storage. Implemented are GeneralBruno Cardoso Lopes2011-05-311-0/+10
| | | | | | | | Dynamic, Initial Exec and Local Exec TLS models. Patch by Sasa Stankovic llvm-svn: 132322
* Define a wrapper node for target constant nodes (tglobaladdr, etc.).Akira Hatanaka2011-05-281-1/+3
| | | | | | Need this to prevent emitting illegal conditional move instructions. llvm-svn: 132240
* Remove MipsTargetLowering::LowerFP_TO_SINT. Patterns for fp_to_sint have alreadyAkira Hatanaka2011-05-251-1/+0
| | | | | | been defined in MipsInstrFPU.td. llvm-svn: 132076
* Custom-lower FCOPYSIGN nodes.Akira Hatanaka2011-05-251-0/+1
| | | | llvm-svn: 132074
* Make the logic for determining function alignment more explicit. No ↵Eli Friedman2011-05-061-3/+0
| | | | | | functionality change. llvm-svn: 131012
* Reverse unnecessary changes made in r129606 and r129608. There is no change ↵Akira Hatanaka2011-04-151-8/+7
| | | | | | in functionality. llvm-svn: 129612
* Fix lines that have incorrect indentation or exceed 80 columns. There is no ↵Akira Hatanaka2011-04-151-7/+8
| | | | | | change in functionality. llvm-svn: 129606
* Add pass that expands pseudo instructions into target instructions after ↵Akira Hatanaka2011-04-151-1/+4
| | | | | | register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions. llvm-svn: 129594
* Added support for FP conditional move instructions and fixed bugs in ↵Akira Hatanaka2011-03-311-8/+4
| | | | | | handling of FP comparisons. llvm-svn: 128650
* Improve div/rem node handling on mips. Patch by Akira HatanakaBruno Cardoso Lopes2011-03-041-1/+5
| | | | llvm-svn: 127034
* Lowers block address. Currently asserts when relocation model is not PIC. ↵Bruno Cardoso Lopes2011-03-041-0/+1
| | | | | | Patch by Akira Hatanaka llvm-svn: 127027
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