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* [MIPS] Fix illegal type assert in single-float modeSimon Atanasyan2018-09-111-3/+8
| | | | | | | | | | | | An fp_to_sint node would be incorrectly lowered to a TruncIntFP node in single-float mode. This would trigger an "Unexpected illegal type!" assert. Patch by Dan Ravensloft. Differential revision: https://reviews.llvm.org/D51810 llvm-svn: 341952
* DAG: Add calling convention argument to calling convention funcsMatt Arsenault2018-07-281-2/+4
| | | | | | | | This seems like a pretty glaring omission, and AMDGPU wants to treat kernels differently from other calling conventions. llvm-svn: 338194
* [mips] Sign extend i32 return values on MIPS64Stefan Maksimovic2018-07-261-0/+7
| | | | | | | | | | | | | Override getTypeForExtReturn so that functions returning an i32 typed value have it sign extended on MIPS64. Also provide patterns to get rid of unneeded sign extensions for arithmetic instructions which implicitly sign extend their results. Differential Revision: https://reviews.llvm.org/D48374 llvm-svn: 338019
* [mips] Fix local dynamic TLS with Sym64Simon Atanasyan2018-07-241-2/+3
| | | | | | | | | | | | | | | | For the final DTPREL addition, rather than a lui/daddiu/daddu triple, LLVM was erronously emitting a daddiu/daddiu pair, treating the %dtprel_hi as if it were a %dtprel_lo, since Mips::Hi expands unshifted for Sym64. Instead, use a new TlsHi node and, although unnecessary due to the exact structure of the nodes emitted, use TlsHi for local exec too to prevent future bugs. Also garbage-collect the unused TprelLo and TlsGd nodes, and TprelHi since its functionality is provided by the new common TlsHi node. Patch by James Clarke. Differential revision: https://reviews.llvm.org/D49259 llvm-svn: 337827
* [mips] Fix atomic operations at O0, v3Aleksandar Beserminji2018-07-051-329/+276
| | | | | | | | | | | | | | | | | | | | | | | Similar to PR/25526, fast-regalloc introduces spills at the end of basic blocks. When this occurs in between an ll and sc, the stores can cause the atomic sequence to fail. This patch fixes the issue by introducing more pseudos to represent atomic operations and moving their lowering to after the expansion of postRA pseudos. This version addresses issues with the initial implementation and covers all atomic operations. This resolves PR/32020. Thanks to James Cowgill for reporting the issue! Patch By: Simon Dardis Differential Revision: https://reviews.llvm.org/D31287 llvm-svn: 336328
* [mips] Modify comment to test new email address (NFC).Simon Dardis2018-06-211-1/+1
| | | | llvm-svn: 335269
* [Mips] Remove uneeded variants of ADDC/ADDE loweringAmaury Sechet2018-06-051-5/+0
| | | | | | | | | | | | Summary: As it turns out, the lowering for the Mips16* family of target is the exact same thing as what the ops expands to, so the code handling them can be removed and the ops only enabled for the MipsSE* family of targets. Reviewers: smaksimovic, atanasyan, abeserminji Subscribers: sdardis, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D47703 llvm-svn: 334052
* Set ADDE/ADDC/SUBE/SUBC to expand by defaultAmaury Sechet2018-06-011-10/+3
| | | | | | | | | | | | | | | Summary: They've been deprecated in favor of UADDO/ADDCARRY or USUBO/SUBCARRY for a while. Target that uses these opcodes are changed in order to ensure their behavior doesn't change. Reviewers: efriedma, craig.topper, dblaikie, bkramer Subscribers: jholewinski, arsenm, jyknight, sdardis, nemanjai, nhaehnle, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, mgrang, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D47422 llvm-svn: 333748
* DAG: Remove redundant version of getRegisterTypeForCallingConvMatt Arsenault2018-05-291-6/+0
| | | | | | | | | | | There seems to be no real reason to have these separate copies. The existing implementations just copy each other for x86. For Mips there is a subtle difference, which is just a bug since it changes based on the context where which one was called. Dropping this version, all tests pass. If I try to merge them to match the removed version, a test fails. llvm-svn: 333440
* [mips] Add microMIPSR6 ll/sc instructions.Simon Dardis2018-05-201-8/+8
| | | | | | | | | | Previously the compiler was using the microMIPSR3 variants, incorrectly. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46948 llvm-svn: 332820
* [mips] Fix how compiler fuse instructions to fmadd/fmsubAleksandar Beserminji2018-04-271-0/+1
| | | | | | | | | | This patch makes compiler does not fuse fmul and fadd/fsub into fmadd/fmsub by default. Instead, -fp-contract=fast option can be used when such behavior is desired. Differential Revision: https://reviews.llvm.org/D46057 llvm-svn: 331033
* [MIPS GlobalISel] Select add i32, i32Petar Jovanovic2018-04-111-0/+7
| | | | | | | | | | | | | Add the minimal support necessary to lower a function that returns the sum of two i32 values. Support argument/return lowering of i32 values through registers only. Add tablegen for regbankselect and instructionselect. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D44304 llvm-svn: 329819
* [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to ↵Craig Topper2018-03-291-1/+1
| | | | | | | | | | | | CodeGen layer. Currently EVT is in the IR layer only because of Function.cpp needing a very small piece of the functionality of EVT::getEVTString(). The rest of EVT is used in codegen making CodeGen a better place for it. The previous code converted a Type* to EVT and then called getEVTString. This was only expected to handle the primitive types from Type*. Since there only a few primitive types, we can just print them as strings directly. Differential Revision: https://reviews.llvm.org/D45017 llvm-svn: 328806
* Fix layering by moving ValueTypes.h from CodeGen to IRDavid Blaikie2018-03-231-1/+1
| | | | | | ValueTypes.h is implemented in IR already. llvm-svn: 328397
* Fix layering of MachineValueType.h by moving it from CodeGen to SupportDavid Blaikie2018-03-231-1/+1
| | | | | | | | | This is used by llvm tblgen as well as by LLVM Targets, so the only common place is Support for now. (maybe we need another target for these sorts of things - but for now I'm at least making them correct & we can make them better if/when people have strong feelings) llvm-svn: 328395
* [mips] Don't create nested CALLSEQ_START..CALLSEQ_END nodes.Simon Dardis2018-03-131-8/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the MIPS O32 ABI, the current call lowering logic naively lowers each call, creating the reserved argument area to hold the argument spill areas for $a0..$a3 and the outgoing parameter area if one is required at each call site. In the case of a sufficently large byval argument, a call to memcpy is used to write the start+16..end of the argument into the outgoing parameter area. This is done within the CALLSEQ_START..CALLSEQ_END of the callee. The CALLSEQ nodes are responsible for performing the necessary stack adjustments. Since the O32/N32/N64 MIPS ABIs do not have a red-zone and writing below the stack pointer and reading the values back is unpredictable, the call to memcpy cannot be hoisted out of the callee's CALLSEQ nodes. However, for the O32 ABI requires the reserved argument area for functions which have parameters. The naive lowering of calls will then create nested CALLSEQ sequences. For N32 and N64 these nodes are also created, but with zero stack adjustments as those ABIs do not have a reserved argument area. This patch addresses the correctness issue by recognizing the special case of lowering a byval argument that uses memcpy. By recognizing that the incoming chain already has a CALLSEQ_START node on it when calling memcpy, the CALLSEQ nodes are not created. For the N32 and N64 ABIs, this is not an issue, as no stack adjustment has to be performed. For the O32 ABI, the correctness reasoning is different. In the case of a sufficently large byval argument, registers a0..a3 are going to be used for the callee's arguments, mandating the creation of the reserved argument area. The call to memcpy in the naive case will also create its own reserved argument area. However, since the reserved argument area consists of undefined values, both calls can use the same reserved argument area. Reviewers: abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D44296 llvm-svn: 327388
* [TLS] use emulated TLS if the target supports only this modeChih-Hung Hsieh2018-02-281-1/+1
| | | | | | | | | | | | | | | Emulated TLS is enabled by llc flag -emulated-tls, which is passed by clang driver. When llc is called explicitly or from other drivers like LTO, missing -emulated-tls flag would generate wrong TLS code for targets that supports only this mode. Now use useEmulatedTLS() instead of Options.EmulatedTLS to decide whether emulated TLS code should be generated. Unit tests are modified to run with and without the -emulated-tls flag. Differential Revision: https://reviews.llvm.org/D42999 llvm-svn: 326341
* [mips] Generate memory dependencies for byVal argumentsStefan Maksimovic2018-02-221-1/+6
| | | | | | | | | | | | | | | | | | | | | There were no memory dependencies made between stores generated when lowering formal arguments and loads generated when call lowering byVal arguments which made the Post-RA scheduler place a load before a matching store. Make the fixed object stored to mutable so that the load instructions can have their memory dependencies added Set the frame object as isAliased which clears the underlying objects vector in ScheduleDAGInstrs::buildSchedGraph(). This results in addition of all stores as dependenies for loads. This problem appeared when passing a byVal parameter coupled with a fastcc function call. Differential Revision: https://reviews.llvm.org/D37515 llvm-svn: 325782
* [MIPS][MSA] Convert vector integer min/max opcodes to use generic implementationSimon Pilgrim2018-02-171-4/+0
| | | | | | | | | | Found while investigating D43338 Simon^3 - the LLVM project needs more Simons. Differential Revision: https://reviews.llvm.org/D43433 llvm-svn: 325447
* [mips] Fix 'l' constraint handling for types smaller than 32 bitsSimon Atanasyan2018-02-121-1/+1
| | | | | | | | | | In case of correct using of the 'l' constraint llvm now generates valid code; otherwise it shows an error message. Initially these triggers an assertion. This commit is the same as r324869 with fixed the test's file name. llvm-svn: 324885
* [mips] Revert rL324869Simon Atanasyan2018-02-121-1/+1
| | | | | | | This commit adds inlineasm-cnstrnt-bad-l.ll which is clashing with inlineasm-cnstrnt-bad-L.ll on case insensitive file systems. llvm-svn: 324882
* [mips] Fix 'l' constraint handling for types smaller than 32 bitsSimon Atanasyan2018-02-121-1/+1
| | | | | | | | In case of correct using of the 'l' constraint llvm now generates valid code; otherwise it shows an error message. Initially these triggers an assertion. llvm-svn: 324869
* Revert accidental changes that snuck in r324584Stefan Maksimovic2018-02-081-5/+0
| | | | llvm-svn: 324585
* [mips] Define certain instructions in microMIPS32r3Stefan Maksimovic2018-02-081-0/+5
| | | | | | | | | | | | | | | | | | | | Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584
* [mips] Fix incorrect sign extension for fpowi libcallSimon Dardis2018-01-301-3/+2
| | | | | | | | | | | | | | | | | PR36061 showed that during the expansion of ISD::FPOWI, that there was an incorrect zero extension of the integer argument which for MIPS64 would then give incorrect results. Address this with the existing mechanism for correcting sign extensions. This resolves PR36061. Thanks to James Cowgill for reporting the issue! Reviewers: atanasyan, hfinkel Differential Revision: https://reviews.llvm.org/D42537 llvm-svn: 323781
* [mips] Provide correct descriptions of asm constraints in the comments. NFCSimon Atanasyan2017-12-291-2/+4
| | | | llvm-svn: 321566
* [mips] Replace assert by an error messageSimon Atanasyan2017-12-291-2/+4
| | | | | | | | Initially, if the `c` constraint applied to the wrong data type that causes LLVM to assert. This commit replaces the assert by an error message. llvm-svn: 321565
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-5/+5
| | | | | | The Function can never be nullptr so we can return a reference. llvm-svn: 320884
* [mips] Removal of microMIPS64R6Aleksandar Beserminji2017-12-111-5/+0
| | | | | | | | | | | All files and parts of files related to microMIPS4R6 are removed. When target is microMIPS4R6, errors are printed. This is LLVM part of patch. Differential Revision: https://reviews.llvm.org/D35625 llvm-svn: 320350
* Use getStoreSize() in various places instead of 'BitSize >> 3'.Jonas Paulsson2017-11-281-2/+1
| | | | | | | | | | | | | | | | | | This is needed for cases when the memory access is not as big as the width of the data type. For instance, storing i1 (1 bit) would be done in a byte (8 bits). Using 'BitSize >> 3' (or '/ 8') would e.g. give the memory access of an i1 a size of 0, which for instance makes alias analysis return NoAlias even when it shouldn't. There are no tests as this was done as a follow-up to the bugfix for the case where this was discovered (r318824). This handles more similar cases. Review: Björn Petterson https://reviews.llvm.org/D40339 llvm-svn: 319173
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-3/+3
| | | | | | | | This header includes CodeGen headers, and is not, itself, included by any Target headers, so move it into CodeGen to match the layering of its implementation. llvm-svn: 317647
* Move TargetFrameLowering.h to CodeGen where it's implementedDavid Blaikie2017-11-031-1/+1
| | | | | | | | | | | This header already includes a CodeGen header and is implemented in lib/CodeGen, so move the header there to match. This fixes a link error with modular codegeneration builds - where a header and its implementation are circularly dependent and so need to be in the same library, not split between two like this. llvm-svn: 317379
* Revert "[mips] Reordering callseq* nodes to be linear"Aleksandar Beserminji2017-10-201-20/+19
| | | | | | | This reverts commit r314507, because the original patch is causing test failures. llvm-svn: 316215
* Remove unused variablesVitaly Buka2017-10-151-1/+0
| | | | llvm-svn: 315847
* [mips] Reordering callseq* nodes to be linearAleksandar Beserminji2017-09-291-19/+20
| | | | | | | | | | | | | Fix nested callseq* nodes by moving callseq_start after the arguments calculation to temporary registers, so that callseq* nodes in resulting DAG are linear. Recommitting r314497. This version does not contain test which fails when compiler is not build in debug mode. Differential Revision: https://reviews.llvm.org/D37328 llvm-svn: 314507
* Revert "[mips] Reordering callseq* nodes to be linear"Aleksandar Beserminji2017-09-291-20/+19
| | | | | | | | | Added test relies on the compiler being built in debug mode, which may not be the case. This reverts commit r314497. llvm-svn: 314506
* [mips] Reordering callseq* nodes to be linearAleksandar Beserminji2017-09-291-19/+20
| | | | | | | | | | Fix nested callseq* nodes by moving callseq_start after the arguments calculation to temporary registers, so that callseq* nodes in resulting DAG are linear. Differential Revision: https://reviews.llvm.org/D37328 llvm-svn: 314497
* [DAGCombiner] fold assertzexts separated by truncSanjay Patel2017-09-181-33/+0
| | | | | | | | | | | | | If we have an AssertZext of a truncated value that has already been AssertZext'ed, we can assert on the wider source op to improve the zext-y knowledge: assert (trunc (assert X, i8) to iN), i1 --> trunc (assert X, i1) to iN This moves a fold from being Mips-specific to general combining, and x86 shows improvements. Differential Revision: https://reviews.llvm.org/D37017 llvm-svn: 313577
* [mips] Lift the assertion on the types that can be used with MipsGPRelSimon Dardis2017-08-111-2/+2
| | | | | | | | | | | | | | | | Post commit review of rL308619 highlighted the need for handling N64 with -fno-pic. Testing reveale a stale assert when generating a GP relative addressing mode. This patch removes that assert and adds the necessary patterns for MIPS64 to perform gp relative addressing with -fno-pic (and the implicit -mno-abicalls + -mgpopt). Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D36472 llvm-svn: 310713
* [Mips] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-08-031-15/+47
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 309993
* Change CallLoweringInfo::CS to be an ImmutableCallSite instead of a pointer. ↵Peter Collingbourne2017-07-261-1/+1
| | | | | | | | NFCI. This was a use-after-free waiting to happen. llvm-svn: 309159
* [SystemZ, LoopStrengthReduce]Jonas Paulsson2017-07-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes LSR generate better code for SystemZ in the cases of memory intrinsics, Load->Store pairs or comparison of immediate with memory. In order to achieve this, the following common code changes were made: * New TTI hook: LSRWithInstrQueries(), which defaults to false. Controls if LSR should do instruction-based addressing evaluations by calling isLegalAddressingMode() with the Instruction pointers. * In LoopStrengthReduce: handle address operands of memset, memmove and memcpy as address uses, and call isFoldableMemAccessOffset() for any LSRUse::Address, not just loads or stores. SystemZ changes: * isLSRCostLess() implemented with Insns first, and without ImmCost. * New function supportedAddressingMode() that is a helper for TTI methods looking at Instructions passed via pointers. Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D35262 https://reviews.llvm.org/D35049 llvm-svn: 308729
* Reland r308585Stefan Maksimovic2017-07-201-29/+2
| | | | | | | | Builder clang-x86_64-linux-abi-test apparently failed due to a spurious error unrelated to the changes r308585 introduced. llvm-svn: 308612
* [mips] Support `long_call/far/near` attributes passed by front-endSimon Atanasyan2017-07-201-9/+24
| | | | | | | | | This patch adds handling of the `long_call`, `far`, and `near` attributes passed by front-end. The patch depends on D35479. Differential revision: https://reviews.llvm.org/D35480. llvm-svn: 308606
* Revert r308585Stefan Maksimovic2017-07-201-2/+29
| | | | | | Builder clang-x86_64-linux-abi-test seems to fail after this change llvm-svn: 308597
* [mips] Fix fp select machine verifier errorsStefan Maksimovic2017-07-201-29/+2
| | | | | | | | | | | | | | | | | Introduced FSELECT node necesary when lowering ISD::SELECT which has i32, f64, f64 as its operands. SEL_D instruction required that its output and first operand of a SELECT node, which it used, have matching types. MTC1_D64 node introduced to aid FSELECT lowering. This fixes machine verifier errors on following tests: CodeGen/Mips/llvm-ir/select-dbl.ll CodeGen/Mips/llvm-ir/select-flt.ll CodeGen/Mips/select.ll Differential Revision: https://reviews.llvm.org/D35408 llvm-svn: 308595
* [mips] Handle the `long-calls` feature flags in the MIPS backendSimon Atanasyan2017-07-151-0/+14
| | | | | | | | | | If the `long-calls` feature flags is enabled, disable use of the `jal` instruction. Instead of that call a function by by first loading its address into a register, and then using the contents of that register. Differential revision: https://reviews.llvm.org/D35168 llvm-svn: 308087
* Reland "[mips] Fix multiprecision arithmetic."Simon Dardis2017-07-131-2/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
* Revert "[mips] Fix multiprecision arithmetic."Simon Dardis2017-06-291-133/+2
| | | | | | | This reverts commit r305389. This broke chromium builds, so reverting while I investigate further. llvm-svn: 306741
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