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path: root/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
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* Move most user of TargetMachine::getDataLayout to the Module oneMehdi Amini2015-07-161-3/+2
| | | | | | | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. This patch is quite boring overall, except for some uglyness in ASMPrinter which has a getDataLayout function but has some clients that use it without a Module (llmv-dsymutil, llvm-dwarfdump), so some methods are taking a DataLayout as parameter. Reviewers: echristo Subscribers: yaron.keren, rafael, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11090 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 242386
* [mips] [IAS] Refactor the emitDirectiveModuleOddSPReg() functions. NFC.Toma Tabacu2015-06-251-2/+1
| | | | | | | | | | | | | | | | | | | Summary: We can simplify emitDirectiveModuleOddSPReg() by having it print the current OddSPReg information from MipsABIFlagsSection and doing an updateABIInfo() before such calls. This prevents us from forgetting to update the STI.FeatureBits, because updateABIInfo() uses those to update the MipsABIFlagsSection object, and also makes sure we use the update mechanism from MipsABIFlagsSection. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D10641 llvm-svn: 240630
* Clean up redundant copies of Triple objects. NFCDaniel Sanders2015-06-161-1/+1
| | | | | | | | | | | | | | Summary: Reviewers: rengolin Reviewed By: rengolin Subscribers: llvm-commits, rengolin, jholewinski Differential Revision: http://reviews.llvm.org/D10382 llvm-svn: 239823
* Replace string GNU Triples with llvm::Triple in ↵Daniel Sanders2015-06-161-1/+2
| | | | | | | | | | | | | | | | | | TargetMachine::getTargetTriple(). NFC. Summary: This continues the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. Reviewers: rengolin Reviewed By: rengolin Subscribers: llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10381 llvm-svn: 239815
* Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and ↵Daniel Sanders2015-06-101-3/+2
| | | | | | | | | | | | | | | | | | create*MCSubtargetInfo(). NFC. Summary: This continues the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. Reviewers: rafael Reviewed By: rafael Subscribers: rafael, ted, jfb, llvm-commits, rengolin, jholewinski Differential Revision: http://reviews.llvm.org/D10311 llvm-svn: 239467
* MC: Add target hook to control symbol quotingMatt Arsenault2015-06-091-2/+2
| | | | llvm-svn: 239370
* Create a MCSymbolELF.Rafael Espindola2015-06-021-3/+4
| | | | | | | | | This create a MCSymbolELF class and moves SymbolSize since only ELF needs a size expression. This reduces the size of MCSymbol from 56 to 48 bytes. llvm-svn: 238801
* MC: Clean up MCExpr naming. NFC.Jim Grosbach2015-05-301-4/+4
| | | | llvm-svn: 238634
* [Mips] Prefer Twine::utohexstr over utohexstr, saves a string copy.Benjamin Kramer2015-05-231-3/+2
| | | | | | NFC. llvm-svn: 238103
* Move alignment from MCSectionData to MCSection.Rafael Espindola2015-05-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This starts merging MCSection and MCSectionData. There are a few issues with the current split between MCSection and MCSectionData. * It optimizes the the not as important case. We want the production of .o files to be really fast, but the split puts the information used for .o emission in a separate data structure. * The ELF/COFF/MachO hierarchy is not represented in MCSectionData, leading to some ad-hoc ways to represent the various flags. * It makes it harder to remember where each item is. The attached patch starts merging the two by moving the alignment from MCSectionData to MCSection. Most of the patch is actually just dropping 'const', since MCSectionData is mutable, but MCSection was not. llvm-svn: 237936
* MC: Clean up method names in MCContext.Jim Grosbach2015-05-181-4/+4
| | | | | | | The naming was a mish-mash of old and new style. Update to be consistent with the new. NFC. llvm-svn: 237594
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-131-8/+8
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* [mips] Emit the .insn directive for empty basic blocks.Vasileios Kalintiris2015-05-081-0/+6
| | | | | | | | | | | | | | | | | | | Summary: In microMIPS, labels need to know whether they are on code or data. This is indicated with STO_MIPS_MICROMIPS and can be inferred by being followed by instructions. For empty basic blocks, we can ensure this by emitting the .insn directive after the label. Also, this fixes some failures in our out-of-tree microMIPS buildbots, for the exception handling regression tests under: SingleSource/Regression/C++/EH Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9530 llvm-svn: 236815
* [AsmPrinter] Make AsmPrinter's OutStreamer member a unique_ptr.Lang Hames2015-04-241-32/+32
| | | | | | | AsmPrinter owns the OutStreamer, so an owning pointer makes sense here. Using a reference for this is crufty. llvm-svn: 235752
* [mips] Refactor saved-registers bitmask creation in ↵Toma Tabacu2015-04-091-20/+11
| | | | | | | | | | | | | | | | | | | MipsAsmPrinter::printSavedRegsBitmask. NFC. Summary: Make the code more readable by fusing the for-loops together and explicitly checking for each register class. Also, this version is more straightforward because it doesn't assume that FPU registers always come before CPU registers in the CalleeSavedInfo vector. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8033 llvm-svn: 234475
* [mips] Distinguish 'R', 'ZC', and 'm' inline assembly memory constraint.Daniel Sanders2015-03-241-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Previous behaviour of 'R' and 'm' has been preserved for now. They will be improved in subsequent commits. The offset permitted by ZC varies according to the subtarget since it is intended to match the restrictions of the pref, ll, and sc instructions. The restrictions on these instructions are: * For microMIPS: 12-bit signed offset. * For Mips32r6/Mips64r6: 9-bit signed offset. * Otherwise: 16-bit signed offset. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8414 llvm-svn: 233063
* Grab the cached subtarget off of the MachineFunction.Eric Christopher2015-03-211-5/+4
| | | | llvm-svn: 232878
* Have the MipsAsmPrinter fp stub emission code take a customEric Christopher2015-02-211-34/+46
| | | | | | | MCSubtargetInfo as the MachineFunction has gone away and we need to emit code at the module level. llvm-svn: 230133
* Turn an if+llvm_unreachable into an assert and reword comment.Eric Christopher2015-02-211-7/+4
| | | | llvm-svn: 230132
* Endianness can be gotten from the DataLayout which we alreadyEric Christopher2015-02-211-1/+1
| | | | | | have. Also, the subtarget is invalid at this point. llvm-svn: 230131
* Get the cached subtarget off the MachineFunction rather thanEric Christopher2015-02-201-1/+1
| | | | | | inquiring for a new one from the TargetMachine. llvm-svn: 230000
* Remove unused argument from emitInlineAsmStart.Eric Christopher2015-02-191-2/+1
| | | | llvm-svn: 229907
* Make the Mips AsmPrinter independent of global subtargetEric Christopher2015-02-181-9/+22
| | | | | | | | | | | | | | initialization. Initialize the subtarget once per function and migrate EmitStartOfAsmFile to either use calls on the TargetMachine or get information from the subtarget we'd use for assembling. The top-level-ness of the MIPS attribute output for assembly is, by nature, contrary to how we'd want to do this for an LTO situation where we have multiple cpu architectures so this solution is good enough for now. llvm-svn: 229596
* Mips: Canonicalize access to function attributes, NFCDuncan P. N. Exon Smith2015-02-141-4/+1
| | | | | | | | | | | | Canonicalize access to function attributes to use the simpler API. getAttributes().getAttribute(AttributeSet::FunctionIndex, Kind) => getFnAttribute(Kind) getAttributes().hasAttribute(AttributeSet::FunctionIndex, Kind) => hasFnAttribute(Kind) llvm-svn: 229221
* Get rid of a few calls through the subtarget to get the ABIEric Christopher2015-01-291-7/+6
| | | | | | that's actually sitting on the target machine. llvm-svn: 227513
* Compute the ELF SectionKind from the flags.Rafael Espindola2015-01-291-9/+7
| | | | | | | | | | | | Any code creating an MCSectionELF knows ELF and already provides the flags. SectionKind is an abstraction used by common code that uses a plain MCSection. Use the flags to compute the SectionKind. This removes a lot of guessing and boilerplate from the MCSectionELF construction. llvm-svn: 227476
* Move DataLayout back to the TargetMachine from TargetSubtargetInfoEric Christopher2015-01-261-1/+1
| | | | | | | | | | | | | | | | | | | derived classes. Since global data alignment, layout, and mangling is often based on the DataLayout, move it to the TargetMachine. This ensures that global data is going to be layed out and mangled consistently if the subtarget changes on a per function basis. Prior to this all targets(*) have had subtarget dependent code moved out and onto the TargetMachine. *One target hasn't been migrated as part of this change: R600. The R600 port has, as a subtarget feature, the size of pointers and this affects global data layout. I've currently hacked in a FIXME to enable progress, but the port needs to be updated to either pass the 64-bitness to the TargetMachine, or fix the DataLayout to avoid subtarget dependent features. llvm-svn: 227113
* Move the Mips target to storing the ABI in the TargetMachine ratherEric Christopher2015-01-261-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | than on MipsSubtargetInfo. This required a bit of massaging in the MC level to handle this since MC is a) largely a collection of disparate classes with no hierarchy, and b) there's no overarching equivalent to the TargetMachine, instead only the subtarget via MCSubtargetInfo (which is the base class of TargetSubtargetInfo). We're now storing the ABI in both the TargetMachine level and in the MC level because the AsmParser and the TargetStreamer both need to know what ABI we have to parse assembly and emit objects. The target streamer has a pointer to the one in the asm parser and is updated when the asm parser is created. This is fragile as the FIXME comment notes, but shouldn't be a problem in practice since we always create an asm parser before attempting to emit object code via the assembler. The TargetMachine now contains the ABI so that the DataLayout can be constructed dependent upon ABI. All testcases have been updated to use the -target-abi command line flag so that we can set the ABI without using a subtarget feature. Should be no change visible externally here. llvm-svn: 227102
* [mips] Add comment which explains why we need to change the assembler ↵Toma Tabacu2015-01-091-0/+6
| | | | | | options before and after inline asm blocks. NFC. llvm-svn: 225521
* Use the same call off of the TargetMachine rather than the subtarget.Eric Christopher2015-01-061-1/+1
| | | | llvm-svn: 225232
* [mips] Set GCC-compatible MIPS asssembler options before inline asm blocks.Toma Tabacu2014-12-171-1/+18
| | | | | | | | | | | | | | | | | | | | Summary: When generating MIPS assembly, LLVM always overrides the default assembler options by emitting the '.set noreorder', '.set nomacro' and '.set noat' directives, while GCC uses the default options if an assembly-level function contains inline assembly code. This becomes a problem when the code generated by LLVM is interleaved with inline assembly which assumes GCC-like assembler options (from Linux, for example). This patch fixes these conflicts by setting the appropriate assembler options at the beginning of an inline asm block and popping them at the end. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6637 llvm-svn: 224425
* [mips][micromips] Implement SWM32 and LWM32 instructionsZoran Jovanovic2014-11-191-0/+20
| | | | | | Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
* [mips] Tolerate the use of the %z inline asm operand modifier with ↵Toma Tabacu2014-11-061-7/+5
| | | | | | | | | | | | | | | | | | | | | | non-immediates. Summary: Currently, we give an error if %z is used with non-immediates, instead of continuing as if the %z isn't there. For example, you use the %z operand modifier along with the "Jr" constraints ("r" makes the operand a register, and "J" makes it an immediate, but only if its value is 0). In this case, you want the compiler to print "$0" if the inline asm input operand turns out to be an immediate zero and you want it to print the register containing the operand, if it's not. We give an error in the latter case, and we shouldn't (GCC also doesn't). Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6023 llvm-svn: 221453
* [mips] Replace MipsABIEnum with a MipsABIInfo class.Daniel Sanders2014-10-241-5/+5
| | | | | | | | | | | | | | | | | | | | | Summary: No functional change yet, it's just an object replacement for an enum. It will allow us to gather ABI information in a single place so that we can start testing for properties of the ABI's instead of the ABI itself. For example we will eventually be able to use: ABI.MinStackAlignmentInBytes() instead of: (isABI_N32() || isABI_N64()) ? 16 : 8 which is clearer and more maintainable. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3341 llvm-svn: 220568
* [mips] Rename [gs]etCanHaveModuleDir to more natural namesDaniel Sanders2014-08-141-1/+1
| | | | | | | | | | | | | | | | | Summary: getCanHaveModuleDir() is renamed to isModuleDirectiveAllowed(), and setCanHaveModuleDir() is renamed to forbidModuleDirective() since it is only ever given a false argument. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D4885 llvm-svn: 215628
* [mips] Initial implementation of -mabicalls/-mno-abicalls.Daniel Sanders2014-08-081-3/+1
| | | | | | | | | | | This patch implements the main rules for -mno-abicalls such as reserving $gp, and emitting the correct .option directive. Patch by Matheus Almeida and Toma Tabacu Differential Revision: http://reviews.llvm.org/D4231 llvm-svn: 215194
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-4/+6
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* [mips] Do not emit '.module fp=...' unless we really need to.Daniel Sanders2014-07-211-10/+15
| | | | | | | | | | | | We now emit this value when we need to contradict the default value. This restores support for binutils 2.24. When a suitable binutils has been released we can resume unconditionally emitting .module directives. This is preferable to omitting the .module directives since the .module directives protect against, for example, accidentally assembling FP32 code with -mfp64 and producing an unusuable object. llvm-svn: 213548
* [mips] Do not emit '.module [no]oddspreg' unless we really need to.Daniel Sanders2014-07-211-3/+8
| | | | | | | | | | | | We now emit this directive when we need to contradict the default value (e.g. -mno-odd-spreg is given) or an option changed the default value (e.g. -mfpxx is given). This restores support for the currently available head of binutils. However, at this point binutils 2.24 is still not sufficient since it does not support '.module fp=...'. llvm-svn: 213511
* Fundamentally change the MipsSubtarget replacement machinery:Eric Christopher2014-07-181-2/+2
| | | | | | | | | | | | | | | | | a) Move the replacement level decision to the target machine. b) Create additional subtargets at the TargetMachine level to cache and make replacement easy. c) Make the mips16 features obvious. d) Remove the override logic as it no longer does anything. e) Have MipsModuleDAGToDAGISel take only the target machine. f) Have the constant islands pass grab the current subtarget from the MachineFunction (via the TargetMachine) instead of caching it. g) Unconditionally initialize TLOF. h) Remove the old complicated subtarget based resetting and replace it with simple conditionals. llvm-svn: 213430
* Reset the Subtarget in the AsmPrinter for each machine functionEric Christopher2014-07-181-1/+3
| | | | | | | and add explanatory comment about dual initialization. Fix use of the Subtarget to grab the information off of the target machine. llvm-svn: 213336
* [mips] Add support for -modd-spreg/-mno-odd-spregDaniel Sanders2014-07-101-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When -mno-odd-spreg is in effect, 32-bit floating point values are not permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit floating point comparison results from being written to odd registers. This option has three purposes: * It allows support for certain MIPS implementations such as loongson-3a that do not allow the use of odd registers for single precision arithmetic. * When using -mfpxx, -mno-odd-spreg is the default and this allows us to statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1 instructions to/from odd registers are guaranteed not to appear for any reason. Once this has been established, the user can then re-enable -modd-spreg to regain the use of all 32 single-precision registers. * When using -mfp64 and -mno-odd-spreg together, an O32 extension named O32 FP64A is used as the ABI. This is intended to provide almost all functionality of an FR=1 processor but can also be executed on a FR=0 core with the assistance of a hardware compatibility mode which emulates FR=0 behaviour on an FR=1 processor. * Added '.module oddspreg' and '.module nooddspreg' each of which update the .MIPS.abiflags section appropriately * Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller doesn't have to remember to do it. * MipsABIFlags now calculates the flags1 and flags2 member on demand rather than trying to maintain them in the same format they will be emitted in. There is one portion of the -mfp64 and -mno-odd-spreg combination that is not implemented yet. Moves to/from odd-numbered double-precision registers must not use mtc1. I will fix this in a follow-up. Differential Revision: http://reviews.llvm.org/D4383 llvm-svn: 212717
* [mips][mips64r6] Use JALR for indirect branches instead of JR (which is not ↵Daniel Sanders2014-07-091-6/+8
| | | | | | | | | | | | | | | | | available on MIPS32r6/MIPS64r6) Summary: This completes the change to use JALR instead of JR on MIPS32r6/MIPS64r6. Reviewers: jkolek, vmedic, zoran.jovanovic, dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D4269 llvm-svn: 212605
* [mips][mips64r6] Use JALR for returns instead of JR (which is not available ↵Daniel Sanders2014-07-091-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on MIPS32r6/MIPS64r6) Summary: RET, and RET_MM have been replaced by a pseudo named PseudoReturn. In addition a version with a 64-bit GPR named PseudoReturn64 has been added. Instruction selection for a return matches RetRA, which is expanded post register allocation to PseudoReturn/PseudoReturn64. During MipsAsmPrinter, this PseudoReturn/PseudoReturn64 are emitted as: - (JALR64 $zero, $rs) on MIPS64r6 - (JALR $zero, $rs) on MIPS32r6 - (JR_MM $rs) on microMIPS - (JR $rs) otherwise On MIPS32r6/MIPS64r6, 'jr $rs' is an alias for 'jalr $zero, $rs'. To aid development and review (specifically, to ensure all cases of jr are updated), these aliases are temporarily named 'r6.jr' instead of 'jr'. A follow up patch will change them back to the correct mnemonic. Added (JALR $zero, $rs) to MipsNaClELFStreamer's definition of an indirect jump, and removed it from its definition of a call. Note: I haven't accounted for MIPS64 in MipsNaClELFStreamer since it's doesn't appear to account for any MIPS64-specifics. The return instruction created as part of eh_return expansion is now expanded using expandRetRA() so we use the right return instruction on MIPS32r6/MIPS64r6 ('jalr $zero, $rs'). Also, fixed a misuse of isABI_N64() to detect 64-bit wide registers in expandEhReturn(). Reviewers: jkolek, vmedic, mseaborn, zoran.jovanovic, dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D4268 llvm-svn: 212604
* [mips] Improve encapsulation of the .MIPS.abiflags implementation and limit ↵Daniel Sanders2014-07-081-12/+3
| | | | | | | | | | | | | | | scope of related enums Summary: Follow on to r212519 to improve the encapsulation and limit the scope of the enums. Also merged two very similar parser functions, fixed a bug where ASE's were not being reported, and marked CPR1's as being 128-bit when MSA is enabled. Differential Revision: http://reviews.llvm.org/D4384 llvm-svn: 212522
* Mips.abiflags is a new implicitly generated section that will be present on ↵Vladimir Medic2014-07-081-1/+16
| | | | | | all new modules. The section contains a versioned data structure which represents essentially information to allow a program loader to determine the requirements of the application. This patch implements mips.abiflags section and provides test cases for it. llvm-svn: 212519
* [mips] Optimize long branch for MIPS64 by removing %higher and %highest.Sasa Stankovic2014-05-271-1/+0
| | | | | | | | | | %higher and %highest can have non-zero values only for offsets greater than 2GB, which is highly unlikely, if not impossible when compiling a single function. This makes long branch for MIPS64 3 instructions smaller. Differential Revision: http://llvm-reviews.chandlerc.com/D3281.diff llvm-svn: 209678
* [mips] Fix MipsLongBranch pass to work when the offset from the branch to theSasa Stankovic2014-04-301-1/+9
| | | | | | | | | | | | | | target cannot be determined accurately. This is the case for NaCl where the sandboxing instructions are added in MC layer, after the MipsLongBranch pass. It is also the case when the code has inline assembly. Instead of calculating offset in the MipsLongBranch pass, use %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions that are resolved during the fixup. This patch also deletes microMIPS test file test/CodeGen/Mips/micromips-long-branch.ll and implements microMIPS CHECKs in a much simpler way in a file test/CodeGen/Mips/longbranch.ll, together with MIPS32 and MIPS64. llvm-svn: 207656
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-1/+1
| | | | llvm-svn: 207197
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
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